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International audience; The lane-keeping assistance design for steer-by-wire road vehicles is a multi-objective control problem that addresses lane tracking, improvement of driver comfort and ensuring vehicle stability. The designed architecture must be sensitive to various driver behaviors, provide assistance to drivers whenever required and ensure a smooth transition of authority between manual and automated driving modes. In this work, we propose a novel shared lane-keeping controller-based on quasi-continuous high-order sliding mode control dealing with the above challenges. The parameters of the controller are characterized by an upper bound estimate of the lateral winds force and the road curvature which acts as disturbances. Using the sharing parameter dependent on the monitored driver attribute, the authority is smoothly transitioned between various modes while accounting for driver behaviors. Experimental results on the SHERPA vehicle simulator shows the real-time implementation feasibility. Extensive results and discussions are provided to demonstrate the effectiveness and the applicability of the proposed controller.

This brief deals with the impact of spin-transfer torque magnetic random access memory (STT-MRAM) cell based on double-barrier magnetic tunnel junction (DMTJ) on the performance of a two-layer multilayer perceptron (MLP) neural network. The DMTJ-based cell is benchmarked against the conventional single-barrier MTJ (SMTJ) counterpart by means of a comprehensive evaluation carried out through a state-of-the-art device-to-algorithm simulation framework. The benchmark is based on the MNIST handwritten dataset, Verilog-A MTJ compact models developed by our group, and 0.8 V FinFET technology. Our results point out that the use of DMTJ-based STT-MRAM cells to implement digital embedded non-volatile memory (eNVM) synaptic core allows write/read energy and latency improvements of about 53%/61% and 66%/17%, respectively, as compared to the SMTJ-based equivalent design. This is achieved by ensuring a reduced area footprint and a learning accuracy of about 91%. Such results make the DMTJ-based STT-MRAM cell a good eNVM option for neuro-inspired computing.

Inference carried out on pre-trained deep neural networks (DNNs) is particularly effective as it does not require re-training and entails no loss in accuracy. Unfortunately, resource-constrained devices such as those in the Internet of Things may need to offload the related computation to more powerful servers, particularly, at the network edge. However, edge servers have limited resources compared to those in the cloud; therefore, inference offloading generally requires dividing the original DNN into different pieces that are then assigned to multiple edge servers. Related approaches in the state of the art either make strong assumptions on the system model or fail to provide strict performance guarantees. This article specifically addresses these limitations by applying distributed assignment to deep neural network inference at the edge. In particular, it devises a detailed model of DNN-based inference, suitable for realistic scenarios involving edge computing. Optimal inference offloading with load balancing is also defined as a multiple assignment problem that maximizes proportional fairness. Moreover, a distributed algorithm for DNN inference offloading is introduced to solve such a problem in polynomial time with strong optimality guarantees. Finally, extensive simulations employing different datasets and DNN architectures establish that the proposed solution significantly improves upon the state of the art in terms of inference time (1.14 to 2.62 times faster), load balance (with a Jain’s fairness index of 0.9), and convergence (one order of magnitude less iterations).

Efficiency and efficacy are desirable properties for any evaluation metric having to do with Standard Dynamic Range (SDR) imaging or with High Dynamic Range (HDR) imaging. However, it is a daunting task to satisfy both properties simultaneously. On the one side, existing evaluation metrics like HDR-VDP 2.2 can accurately mimic the Human Visual System (HVS), but this typically comes at a very high computational cost. On the other side, computationally cheaper alternatives (e.g., PSNR, MSE, etc.) fail to capture many crucial aspects of the HVS. In this work, we present NoR-VDPNet++, a deep learning architecture for converting full-reference accurate metrics into no-reference metrics thus reducing the computational burden. We show NoR-VDPNet++ can be successfully employed in different application scenarios.

The novel concept of Factory-as-a-Service~(FaaS) allows the agility of adapting the manufacturing process by identifying the industry's supply chain and user requirements. To cater to FaaS, flexibility in networking and cloud services is a must. 5G network slice broker is a third-party mediator that caters to networking resource demand from clients to the service providers. Thus, this paper introduces a secure blockchain-based network slice broker to facilitate FaaS. The proposed secure network slice broker (SNSB) provides secure, cognitive, and distributed network services for resource allocation and security service level agreement (SSLA) formation with coordination of slice managers and SSLA managers. In SNSB we introduce a federated slice selection algorithm with Stackelberg game model and Reinforcement Learning~(RL) algorithm to compute the real-time and the optimal unit price and demand level. Moreover, we provide an extensive implementation and performance evaluation of SNSB using the Katana slice manager and a custom SSLA manager. Check citation details

In this paper, we examine the influence of communication latency on performance of networked control systems. Even though distributed control architectures offer advantages in terms of communication, maintenance costs, and scalability, it is an open question how communication latency that varies with network topology influences closed-loop performance. For networks in which delays increase with the number of links, we establish the existence of a fundamental performance trade-off that arises from control architecture. In particular, we utilize consensus dynamics with single- and double-integrator agents to show that, if delays increase fast enough, a sparse controller with nearest neighbor interactions can outperform the centralized one with all-to-all communication topology., Comment: 12 pages, 13 figures; accepted for publication on IEEE Transactions on Control of Network Systems; final accepted version

The study pioneers in proposing a hybrid cloud-based framework for designing a totally stand-alone, green residential house, stable over load variations and fluctuations of renewable energy sources (RES). The framework uses wind turbine (WT) and photovoltaic panels (PV) as the main power supplies, while employing a fuel cell (FC), fed with an electrolyzer, as the secondary source of energy. A battery is also used, which together with the FC and electrolyzer, constitute the compensation system in the proposed framework. Taking into account the various types of residential electrical loads, including an electrical vehicle (EV), and applying a deep learning method, the proposed framework makes the day-ahead scheduling of all components in the house based on the forecasted profile of load demand and the energy generated by the RES. The compensation system comes into use to balance the real-time scheduling error caused by the uncertainties of the main sources of power. To ascertain the practicality of the proposed framework for real-life implementation, it is examined on a residential house considering components with authentic technical features. The real-time operation of the suggested residential system is also tested on the SpeadGoat real-time simulator, whose results corroborate the practicability of both the real-time and day-ahead operation of the proposed framework.

International audience; Hyperspectral images (HSIs) are of crucial importance in order to better understand features from a large number of spectral channels. Restricted by its inner imaging mechanism, the spatial resolution is often limited for HSIs. To alleviate this issue, in this work, we propose a simple and efficient architecture of deep convolutional neural networks to fuse a low-resolution HSI (LR-HSI) and a high-resolution multispectral image (HR-MSI), yielding a high-resolution HSI (HR-HSI). The network is designed to preserve both spatial and spectral information thanks to a new architecture based on: 1) the use of the LR-HSI at the HR-MSI’s scale to get an output with satisfied spectral preservation and 2) the application of the attention and pixelShuffle modules to extract information, aiming to output high-quality spatial details. Finally, a plain mean squared error loss function is used to measure the performance during the training. Extensive experiments demonstrate that the proposed network architecture achieves the best performance (both qualitatively and quantitatively) compared with recent state-of-the-art HSI super-resolution approaches. Moreover, other significant advantages can be pointed out by the use of the proposed approach, such as a better network generalization ability, a limited computational burden, and the robustness with respect to the number of training samples. Please find the source code and pretrained models from https://liangjiandeng.github.io/Projects_Res/HSRnet_2021tnnls.html .

Modularity is often employed to increase the flexibility and adaptability of a system. A well-known issue during the design of modular systems is the emergence of ripple effects propagating throughout the system when one module is changed, which is dependent on other modules within the system. While several techniques or approaches have been proposed to mitigate these effects, they often neglect the integration and interconnection of cross-cutting concerns (i.e., functionalities that are required across different parts of the main functional dimension) within the system. This article argues that the proper integration of cross-cutting concerns is important in order to avoid ripple effects and preserve the adaptability of a modular system. Based on a set of possible integration architectures that offer different alternatives to integrate cross-cutting concerns within a modular structure, we introduce the integration design matrix (IDM) as an instrument to systematically analyze the cross-cutting concern provisioning within specific modular artifacts. A set of design guidelines is proposed to optimize the integration of the cross-cutting concerns, applicable within the context of the IDM. We illustrate our approach by means of examples in several domains. Published in: IEEE Transactions on

Scene understanding plays a crucial role in autonomous driving by utilizing sensory data for contextual information extraction and decision making. Beyond modeling advances, the enabler for vehicles to become aware of their surroundings is the availability of visual sensory data, which expand the vehicular perception and realizes vehicular contextual awareness in real-world environments. Research directions for scene understanding pursued by related studies include person/vehicle detection and segmentation, their transition analysis, lane change, and turns detection, among many others Unfortunately, these tasks seem insufficient to completely develop fully-autonomous vehicles i.e. achieving level-5 autonomy, travelling just like human-controlled cars. This latter statement is among the conclusions drawn from this review paper: scene understanding for autonomous driving cars using vision sensors still requires significant improvements. With this motivation, this survey defines, analyzes, and reviews the current achievements of the scene understanding research area that mostly rely on computationally complex deep learning models. Furthermore, it covers the generic scene understanding pipeline, investigates the performance reported by the state-of-the-art, informs about the time complexity analysis of avant garde modeling choices, and highlights major triumphs and noted limitations encountered by current research efforts. The survey also includes a comprehensive discussion on the available datasets, and the challenges that, even if lately confronted by researchers, still remain open to date. Finally, our work outlines future research directions to welcome researchers and practitioners to this exciting domain. This work was supported by the European Commission through European Union (EU) and Japan for Artificial Intelligence (AI) under Grant 957339.

As an important and challenging problem, multidomain learning (MDL) typically seeks a set of effective lightweight domain-specific adapter modules plugged into a common domain-agnostic network. Usually, existing ways of adapter plugging and structure design are handcrafted and fixed for all domains before model learning, resulting in learning inflexibility and computational intensiveness. With this motivation, we propose to learn a data-driven adapter plugging strategy with neural architecture search (NAS), which automatically determines where to plug for those adapter modules. Furthermore, we propose an NAS-adapter module for adapter structure design in an NAS-driven learning scheme, which automatically discovers effective adapter module structures for different domains. Experimental results demonstrate the effectiveness of our MDL model against existing approaches under the conditions of comparable performance.

The staggering innovations and emergence of numerous deep learning (DL) applications have forced researchers to reconsider hardware architecture to accommodate fast and efficient application-specific computations. Applications, such as object detection, image recognition, speech translation, as well as music synthesis and image generation, can be performed with high accuracy at the expense of substantial computational resources using DL. Furthermore, the desire to adopt Industry 4.0 and smart technologies within the Internet of Things infrastructure has initiated several studies to enable on-chip DL capabilities for resource-constrained devices. Specialized DL processors reduce dependence on cloud servers, improve privacy, lessen latency, and mitigate bandwidth congestion. As we reach the limits of shrinking transistors, researchers are exploring various application-specific hardware architectures to meet the performance and efficiency requirements for DL tasks. Over the past few years, several software optimizations and hardware innovations have been proposed to efficiently perform these computations. In this article, we review several DL accelerators, as well as technologies with emerging devices, to highlight their architectural features in application-specific integrated circuit (IC) and field-programmable gate array (FPGA) platforms. Finally, the design considerations for DL hardware in portable applications have been discussed, along with some deductions about the future trends and potential research directions to innovate DL accelerator architectures further. By compiling this review, we expect to help aspiring researchers widen their knowledge in custom hardware architectures for DL. 2012 IEEE. This work was supported in part by the Research University Grant, Universiti Kebangsaan Malaysia, under Grant DPK-2021-001, Grant DIP-2020-004, and Grant MI-2020-002; and in part by the Qatar National Research Foundation (QNRF) under Grant NPRP12s-0227- 190164. Scopus

Shared mobility services require accurate demand models for effective service planning. On the one hand, modeling the full probability distribution of demand is advantageous because the entire uncertainty structure preserves valuable information for decision-making. On the other hand, demand is often observed through the usage of the service itself, so that the observations are censored, as they are inherently limited by available supply. Since the 1980s, various works on Censored Quantile Regression models have performed well under such conditions. Further, in the last two decades, several papers have proposed to implement these models flexibly through Neural Networks. However, the models in current works estimate the quantiles individually, thus incurring a computational overhead and ignoring valuable relationships between the quantiles. We address this gap by extending current Censored Quantile Regression models to learn multiple quantiles at once and apply these to synthetic baseline datasets and datasets from two shared mobility providers in the Copenhagen metropolitan area in Denmark. The results show that our extended models yield fewer quantile crossings and less computational overhead without compromising model performance.

The small satellite (SmallSat) industry has recorded incredible growth recently. Within this class, among mini-, micro-, and nanosatellites, the cube satellite (CubeSat) is primed for an explosion of growth. These satellites are fascinating for remote sensing, Earth observation, and scientific applications. Remarkable attention from the space operators makes it valuable because of its low cost, cubic shape, less manufacturing time, lightweight, and modular structure. Among the various subsystems comprising the SmallSat, the electrical power system (EPS) is the most crucial one because unreliable power supply to the rest is most of the time detrimental to the mission. The EPS is formed by electrical sources, storage units, and loads, all interconnected via different power converters, the operation of which must be closely orchestrated to accomplish efficient use of photovoltaic power, optimal battery management, and resilient power delivery. At the same time, the EPS design must address a series of challenges such as size restrictions, high power density, and harsh space environments (e.g., atomic oxygen, radiation, and extreme temperatures), which significantly impact the EPS electrical and electronic equipment. In terms of power systems, a SmallSat EPS can be considered a space microgrid owing to coordination and control of distributed generation, storage, and loads in a small-scale electrical network. From this point of view, this article reviews and explores SmallSat microgrid's research developments, energy transfer and architectures, converter topologies, latest technologies, main challenges, and some potential solutions, which will enable building a more robust, resilient, and efficient EPS. The research gaps and future developments are underlined before this article is concluded.

There is a widely held belief that future Radio Access Network (RAN) architectures will be characterized by increased levels of virtualization, whereby base station functionalities, traditionally residing at a single location, will be scattered across different logical entities while being interfaced via high-speed fronthaul (FH) links. For the deployment of such FH links, operators are faced with the challenge of maintaining acceptable radio access performance while at the same time keeping deployment costs low. A common practice is to exploit statistical multiplexing by allowing several cells to utilize the same FH link. As a result, in order to cope with the resulting aggregated traffic, different techniques can be used to reduce the required FH data rates. Herein, we focus on FH compression control strategies for multiple-cell/multiple-user scenarios sharing a common FH link. We propose various methods for sounding reference signal (SRS) handling and analyze different FH-aware modulation data compression and scheduling strategies. Considering a full system setup, including the radio and FH access networks, numerical evaluation is conducted using a 5G NR system-level simulator implemented in ns-3. Simulation results show that, under stringent FH capacity constraints, optimized modulation compression strategies provide significant user-perceived throughput gains over baseline strategies (between 5.2x and 6.9x). On top of them, SRS handling methods achieve additional 2% to 41% gains., paper to appear in IEEE Communications Magazine

Nowadays, two groundbreaking factors are emerging in neural networks. Firstly, there is the RISC-V open instruction set architecture (ISA) that allows a seamless implementation of custom instruction sets. Secondly, there are several novel formats for real number arithmetic. In this work, we combined these two key aspects using the very promising posit format, developing a light Posit Processing Unit. We present an extension of the base RISC-V ISA that allows the conversion between 8 or 16-bit posits and 32-bit IEEE Floats or fixed point formats in order to offer a compressed representation of real numbers with little-to-none accuracy degradation. Then we elaborate on the hardware and software toolchain integration of our PPU inside the Ariane RISC-V core and its toolchain, showing how little it impacts in terms of circuit complexity and power consumption. Indeed, only 0.36% of the circuit is devoted to the PPU while the full RISC-V core occupies the 33% of the overall circuit complexity. Finally we present the impact of our PPU-light on a deep neural network task, reporting speedups up to 10 on sample inference processing time.

Demand for coarse grain reconfigurable architectures (CGRAs) has significantly increased in recent years as architectures need to be both energy efficient and flexible. However, most CGRAs are optimized for performance instead of energy efficiency. In this work a novel paradigm for reconfigurable architectures, Blocks, is presented. Blocks uses two separate circuit-switched networks, one for control and one for the data-path. This enables run-time construction of energy-efficient application-specific VLIW-SIMD processors on a reconfigurable fabric. Its energy efficiency is demonstrated by comparing Blocks to four reference architectures, a VLIW, an SIMD, a commercial low-power microprocessor, and a traditional CGRA. All comparisons are based on commercial low-power 40nm CMOS layout, including memories. Results show that Blocks can achieve a mean total energy reduction of 2.05x, 1.84x, 8.01x, 1.22x over a VLIW, an SIMD, an energy-efficient microprocessor and a traditional CGRA respectively. At the same time, Blocks delivers equal or higher performance per area due to its ability to adapt to applications by reconfiguration.

Neuromorphic computing chips consisting of crossbar arrays of emergent non-volatile memory have the potential of achieving both high energy efficiency and throughput as low power implementation of convolutional neural network (CNN) inference engines. However, such hardware has design constraints such as its limited fan-in/fan-out and resource-inefficient mapping that make the design and deployment of CNN on them challenging. As a result, the user has to design the CNN model with intricate knowledge of the hardware architecture and even cannot fit the models in the hardware for CNN with high resolution image input. In this paper, we propose the use of aggregated sub-nets, NC-net, which is a constrained form of the traditional layer structure, to solve these issues. With our method, we put forward an energy-efficient buffer-and ADC/DAC-free (Digital-to-Analogue Converter and Analogueto-Digital Converter) architecture and a scalable end-to-end solution that automatically satisfies the hardware constraints of crossbar architectures, while optimizing the resource usage. In our solution, the exploration and deployment of a CNN for a neuromorphic crossbar hardware starts with a design front-end based on TensorFlow. Our automated design flow maps the NCnet network from TensorFlow to the crossbar architecture. We tested our designs on both a simulator and a field-programmable gate array (FPGA) emulator with various benchmarks. In addition to general benchmarks including MNIST, SVHN, CIFAR-10 and CIFAR-100, we tested our system on a real-world application, human detection with high resolution (224×224) images as input. Our system achieves the state-of-the-art accuracy for these benchmarks on the crossbar-based neuromorphic hardware, with an accuracy of more than 90% for the latter. It also yielded up to 4:25× improvement in the efficiency of spiking core usage compared to TrueNorth.

International audience; A common problem of the virtualized cloud radio access network architecture (C-RAN) is the compression of the time-domain IQ samples before transmission over the fronthaul link. Considering a multicarrier waveform such as OFDM, whose IQ samples follow a quasi-Gaussian distribution, the conventional Gaussian quantizer may be used as the optimal solution to the compression problem. However, since the high peak-to-average power ratio (PAPR) of OFDM signals remains a serious problem, various techniques may be employed to reduce the time-domain fluctuations of the IQ samples in the OFDM, resulting in a change in its distribution. The latter fact makes the Gaussian quantizer suboptimal. The literature lacks a performance analysis of the conventional OFDM-based compression techniques when the PAPR of the OFDM signal is reduced. Therefore, in this paper, we study for the first time the impact of reducing the PAPR of the OFDM signal before compression in the C-RAN architecture through rate-distortion analysis. We consider clipping and tone reservation PAPR reduction algorithms. The former is the simplest PAPR reduction approach, while the latter is one of the most effective algorithms used in broadcasting standards such as DVB-T2 and ATSC 3.0. We first derive the distribution of the PAPR-reduced OFDM IQ samples. This is used to optimize the thresholds and codebook levels of a non-uniform scalar quantizer and the number of quantization bits allocated for each quantized level in the entropy coding stage, along with the MER performance analysis. The simulation results show that the conventional Gaussian-based compression techniques applied to a PAPR-reduced signal is not very robust to the statistical changes in the signal unless the signal distribution at the input of the Gaussian quantizer is not significantly affected. However, a significant gain is obtained when the quantizer is optimized with respect to the true distribution of the PAPR-reduced IQ samples.

Universal and fault-tolerant quantum computation is a promising new paradigm that may efficiently conquer difficult computation tasks beyond the reach of classical computation. It motivates the development of various quantum technologies. The rapid progress of quantum technologies accelerates the realization of quantum computers. In this paper, we survey the recent advances in quantum technologies and quantum computation from the design automation perspective.

The design of large devices suggests fundamental and efficient innovation in Field Programmable Gate Array (FPGA) interconnect structure to improve power consumption, density and performance. Mesh-based FPGA architectures are generally designed to maximize logic utilization and to ensure layout scalability whereas Tree-based FPGA architectures are designed to increase interconnect utilization. In this paper, we propose a new Mesh of Trees (MoTs) FPGA architecture where we try to benefit from Mesh of Clusters (MoCs) FPGA layout scalability and Tree-based FPGA efficient intra-cluster interconnect utilization thanks to Butterfly Fat Tree (BFT) topology. In order to attain the efficient use of the proposed routing interconnect resources, we develop Computer-Aided Design (CAD) tools that respond to the target MoTs FPGA features. In addition, we define the power, area and delay metric models according to the proposed architecture criteria. Experimentation results show that MoTs architecture with a cluster arity 32 offers the best trade-off between power, area and delay. Furthermore, we conduct a comparison between MoTs and MoCs FPGAs in general and the best MoTs and MoCs solutions which ensure the best trade-off between power, area and delay in particular. Results show that the best MoTs architecture reduces power, area, delay and energy by an average of 29%, 6%, 40% and 47%, respectively in comparison with the best MoCs architecture.

Due to the huge success and rapid development of convolutional neural networks (CNNs), there is a growing demand for hardware accelerators that accommodate a variety of CNNs to improve their inference latency and energy efficiency, in order to enable their deployment in real-time applications. Among popular platforms, field-programmable gate arrays (FPGAs) have been widely adopted for CNN acceleration because of their capability to provide superior energy efficiency and low-latency processing, while supporting high reconfigurability, making them favorable for accelerating rapidly evolving CNN algorithms. This article introduces a highly customized streaming hardware architecture that focuses on improving the compute efficiency for streaming applications by providing full-stack acceleration of CNNs on FPGAs. The proposed accelerator maps most computational functions, that is, convolutional and deconvolutional layers into a singular unified module, and implements the residual and concatenative connections between the functions with high efficiency, to support the inference of mainstream CNNs with different topologies. This architecture is further optimized through exploiting different levels of parallelism, layer fusion, and fully leveraging digital signal processing blocks (DSPs). The proposed accelerator has been implemented on Intel's Arria 10 GX1150 hardware and evaluated with a wide range of benchmark models. The results demonstrate a high performance of over 1.3 TOP/s of throughput, up to 97% of compute [multiply-accumulate (MAC)] efficiency, which outperforms the state-of-the-art FPGA accelerators.

Resistive-RAM (RRAM) based deep neural network (DNN) accelerator has shown great potential as it is good at the matrix-vector multiplication (MVM) operator. However, it does not benefit non-MVM operators, such as transcendental activation or element-wise operations, which often require customized CMOS circuits in conventional DNN accelerator designs. In this paper, we propose a new RRAM-based DNN inference accelerator, which leverages the proposed RRAM-CORDIC and RRAM-MLP algorithms to make the transcendental and element-wise operators calculable in the RRAM crossbar just like MVM. Both algorithms can exploit the higher MAC (multiply-and-accumulation) parallelism that is traditionally expensive in CMOS but now efficient in the RRAM crossbar. Then we further propose an inter-crossbar pipelining scheme, which can balance the number of crossbars for MVM and non-MVM operations and orchestrate them in pursuing higher DNN computing throughput. The experiment results show that both algorithms can sustain a high arithmetic accuracy, and deliver less than 1% DNN accuracy loss on typical inference workloads. The elimination of expensive CMOS circuits, in turn, can trade more crossbar resources in the same area to speed up the performance by 1.16X to 2.33X. With the extended operators, the RRAM-based DNN accelerator can switch crossbar functions at will, and apply for a diverse of DNN models in a unified in-memory accelerator architecture.

Edge Computing has emerged as a new computing paradigm dedicated for mobile applications for performance enhancement and energy efficiency purposes. Specifically, it benefits today's interactive applications on power-constrained devices by offloading compute-intensive tasks to the edge nodes which is in close proximity. Meanwhile, Field Programmable Gate Array (FPGA) is well known for its excellence in accelerating compute-intensive tasks such as deep learning algorithms in a high performance and energy efficiency manner due to its hardware-customizable nature. In this paper, we make the first attempt to leverage and combine the advantages of these two, and proposed a new network-assisted computing model, namely FPGA-based edge computing. As a case study, we choose three computer vision (CV)-based mobile interactive applications, and implement their backend computation engines on FPGA. By deploying such application-customized accelerator modules for computation offloading at the network edge, we experimentally demonstrate that this approach can effectively reduce response time for the applications and energy consumption for the entire system in comparison with traditional CPU-based edge/cloud offloading approach.

The further exploration of the neural mechanisms underlying the biological activities of the human brain depends on the development of large-scale spiking neural networks (SNNs) with different categories at different levels, as well as the corresponding computing platforms. Neuromorphic engineering provides approaches to high-performance biologically plausible computational paradigms inspired by neural systems. In this article, we present a biological-inspired cognitive supercomputing system (BiCoSS) that integrates multiple granules (GRs) of SNNs to realize a hybrid compatible neuromorphic platform. A scalable hierarchical heterogeneous multicore architecture is presented, and a synergistic routing scheme for hybrid neural information is proposed. The BiCoSS system can accommodate different levels of GRs and biological plausibility of SNN models in an efficient and scalable manner. Over four million neurons can be realized on BiCoSS with a power efficiency of 2.8k larger than the GPU platform, and the average latency of BiCoSS is 3.62 and 2.49 times higher than conventional architectures of digital neuromorphic systems. For the verification, BiCoSS is used to replicate various biological cognitive activities, including motor learning, action selection, context-dependent learning, and movement disorders. Comprehensively considering the programmability, biological plausibility, learning capability, computational power, and scalability, BiCoSS is shown to outperform the alternative state-of-the-art works for large-scale SNN, while its real-time computational capability enables a wide range of potential applications.

Reinforcement learning (RL) has shown great performance in solving sequential decision-making problems. This paper proposes a framework to train RL agents conditioned on constraints that are in the form of structured language to improve training efficiency. We implemented an energy-efficient hardware accelerator to receive both images and text inputs that allows RL agents understand human language and act in real-world environments. A scalable and parallel hardware with different number of processing elements is implemented on both FPGA and ASIC that provides a balance between power consumption and performance. The post-layout ASIC design consumes 9.2 mW while providing 361 fps throughput.

The tremendous growth in deep learning (DL) applications has created an exponential demand for computing power, which leads to the rise of AI-specific hardware. Targeted towards accelerating computation-intensive deep learning applications, AI hardware, including but not limited to GPGPU, TPU, ASICs, etc., have been adopted ubiquitously. As a result, domainspecific CAD tools play more and more important roles and have been deeply involved in both the design and compilation stages of modern AI hardware. Recently, ISPD 2020 contest introduced a special challenge targeting at the physical mapping of neural network workloads onto the largest commercial deep learning accelerator, CS-1 Wafer-Scale Engine (WSE). In this paper, we proposed CU.POKer, a high-performance engine fullycustomized for WSE’s DNN workload placement challenge. A provably optimal placeable kernel candidate searching scheme and a data-flow-aware placement tool are developed accordingly to ensure the state-of-the-art quality on the real industrial benchmarks. Experimental results on ISPD 2020 contest evaluation suites demonstrated the superiority of our proposed framework over not only the state-of-the-art (SOTA) placer but also the conventional heuristics used in general floorplanning.

Deep neural network (DNN) based video analysis has become one of the most essential and challenging tasks to capture implicit information from video streams. Although DNNs significantly improve the analysis quality, they introduce intensive compute and memory demands and require dedicated hardware for efficient processing. The customized heterogeneous system is one of the promising solutions with general-purpose processors (CPUs) and specialized processors (DNN Accelerators). Among various heterogeneous systems, the combination of CPU and FPGA has been intensively studied for DNN inference with improved latency and energy consumption compared to CPU + GPU schemes and with increased flexibility and reduced time-to-market cost compared to CPU + ASIC designs. However, deploying DNN-based video analysis on CPU + FPGA systems still presents challenges from the tedious RTL programming, the intricate design verification, and the time-consuming design space exploration. To address these challenges, we present a novel framework, called EcoSys, to explore co-design and optimization opportunities on CPU-FPGA heterogeneous systems for accelerating video analysis. Novel technologies include 1) a coherent memory space shared by the host and the customized accelerator to enable efficient task partitioning and online DNN model refinement with reduced data transfer latency; 2) an end-to-end design flow that supports high-level design abstraction and allows rapid development of customized hardware accelerators from Python-based DNN descriptions. 3) a design space exploration (DSE) engine that determines the design space and explores the optimized solutions by considering the targeted heterogeneous system and user-specific constraints; and 4) a complete set of co-optimization solutions, including a layer-based pipeline, a feature map partition scheme, and an efficient memory hierarchical design for the accelerator and multi-threading programming for the CPU. In this paper, we demonstrate our design framework to accelerate the long-term recurrent convolution network (LRCN), which analyzes the input video and output one semantic caption for each frame. EcoSys can deliver 314.7 and 58.1 frames per second (FPS) by targeting the LRCN model with AlexNet and VGG-16 backbone, respectively. Compared to the multithreaded CPU and pure FPGA design, EcoSys achieves 20.6× and 5.3× higher throughput performance.

The ability to support multitasking becomes more and more important in the development of graphic processing unit (GPU). GPU multitasking methods are classified into three types: temporal multitasking, spatial multitasking, and simultaneous multitasking (SMK). This article first introduces the features of some commercial GPU architectures to support multitasking and the common metrics used for evaluating the performance of GPU multitasking methods, and then reviews the GPU multitasking methods supported by hardware architecture (i.e., hardware GPU multitasking methods). The main problems of each type of hardware GPU multitasking methods to be solved are illustrated. Meanwhile, the key idea of each previous hardware GPU multitasking method is introduced. In addition, the characteristics of hardware GPU multitasking methods belonging to the same type are compared. This article also gives some valuable suggestions for the future research. An enhanced GPU simulator is needed to bridge the gap between academia and industry. In addition, it is promising to expand the research space with machine learning technologies, advanced GPU architectural innovations, 3D stacked memory, etc. Because most previous GPU multitasking methods are based on NVIDIA GPUs, this article focuses on NVIDIA GPU architecture, and uses NVIDIA's terminology. To our knowledge, this article is the first survey about hardware GPU multitasking methods. We believe that our survey can help the readers gain insights into the research field of hardware GPU multitasking methods.

The AI chips increasingly focus on implementing neural computing at low power and cost. The intelligent sensing, automation, and edge computing applications have been the market drivers for AI chips. Increasingly, the generalisation, performance, robustness, and scalability of the AI chip solutions are compared with human-like intelligence abilities. Such a requirement to transit from application-specific to general intelligence AI chip must consider several factors. This paper provides an overview of this cross-disciplinary field of study, elaborating on the generalisation of intelligence as understood in building artificial general intelligence (AGI) systems. This work presents a listing of emerging AI chip technologies, classification of edge AI implementations, and the funnel design flow for AGI chip development. Finally, the design consideration required for building an AGI chip is listed along with the methods for testing and validating it.

Contemporary digital infrastructures and systems use and trust PKC to exchange keys over insecure communication channels. With the development and progress in the research field of quantum computers, well established schemes like RSA and ECC are more and more threatened. The urgent demand to find and standardize new schemes - which are secure in a post-quantum world - was also realized by the NIST which announced a PQC Standardization Project in 2017. Recently, the round three candidates were announced and one of the alternate candidates is the KEM scheme BIKE. In this work, we investigate different strategies to efficiently implement the BIKE algorithm on FPGA. To this extend, we improve already existing polynomial multipliers, propose efficient strategies to realize polynomial inversions, and implement the BGF decoder for the first time. Additionally, our implementation is designed to be scalable and generic with the BIKE specific parameters. All together, the fastest designs achieve latencies of 2.69 ms for the key generation, 0.1 ms for the encapsulation, and 1.89 ms for the decapsulation considering the lowest security level.