Search

We compare the contact characteristics for Mo, Pd, and Ti on n-InGaAs layer with a range of active donor concentration from $1.6 \times 10^{18}$ cm−3 to $4.8 \times 10^{19}$ cm−3. The Fermi level pinning of 0.18 eV lower than the bottom of n-InGaAs conduction band is experimentally manifested. It is also revealed that the contact resistivity ( $\rho _{\text {c}}$ ) of Mo/n-InGaAs contact clearly outperforms after annealing. However, for the first time, we demonstrate that the Mo/Pd (2nm)/n-InGaAs contact can achieve a $\rho _{\text {c}}~35$ % and 20% lower than a single Mo/n-InGaAs contact after annealing at 400 °C and 450 °C for 1min, respectively.

The aim of this review paper is to describe the impact of so-called border traps (BTs) in high- k gate oxides on the operation and reliability of high-mobility channel transistors. First, a brief summary of the physics of BTs will be given, describing the charge trapping and release in terms of the elastic tunneling model. It will be also pointed out how information on the BT properties can be extracted from popular measurement techniques such as low-frequency (1/f) noise and variable-frequency charge pumping. In the next two parts, the impact of BTs on metal-oxide-semiconductor structures fabricated on Ge or III-V channel materials is outlined, with particular emphasis on the development of novel or adapted measurement techniques such as AC transconductance dispersion or trap spectroscopy by charge injection and sensing. Finally, the effect of BTs on the operation and reliability of high-mobility channel MOSFETs is discussed. It is also shown that the density of BTs is closely linked to the quality or defectivity of the high- k gate stack, indicating room for improvement by optimization of processing or by implementation of a suitable bulk-oxide defect passivation step.

In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated on 300mm Si substrates. For an \(L_{\mathrm {\mathbf {G}}}\) of 60 nm an extrinsic \(g_{\mathrm {\mathbf {m}}}\) of \(1030~\mu \) S \(/\mu \) m at \(V_{\mathrm {\mathbf {ds}}} = 0.5\) V is achieved which is a \(1.75\times \) increase compared with the replacement fin FinFet process. This improvement is attributed to the elimination of Mg counterdoping in the GAA flow. Ultrascaled nanowires with diameters of 6 nm were demonstrated to show immunity to \(D_{\mathrm {{it}}}\) resulting in an SS \(_{\mathrm {{SAT}}}\) of 66 mV/decade and negligible drain-induced barrier lowering for 85-nm \(L_{\mathrm {{G}}}\) devices.

Trap spectroscopy by charge injection and sensing method was applied to the In0.53Ga0.47As-Al2O3 system, yielding the spatial and energetic distribution of the traps inside the Al2O3 layer. The trap density inside the atomic-layer-deposited (ALD) Al2O3 layer was found to be significantly reduced by (NH4)2S treatment of the InGaAs surface prior to the Al2O3 deposition. Indium concentration inside the Al2O3 layer was found to be reduced once the InGaAs surface is (NH4)2S treated prior to the Al2O3 deposition as measured by time-of-flight secondary ion mass spectroscopy, indicating indium as a possible origin of the oxide traps. The results suggest a new mechanism for the sulfur action at the InGaAs surface, which might be responsible for the transistor performance improvements observed after ( NH4)2S passivation. This mechanism involves sulfur as an indium diffusion/segregation barrier stabilizing the InGaAs surface during the ALD Al2O3 deposition, lowering the oxide trap density. This, in turn, improves the electron mobility through a reduction in the Coulomb scattering of the carriers due to border traps and improves the device drive current.

We introduce an ac transconductance dispersion method (ACGD) to profile the oxide traps in an MOSFET without needing a body contact. The method extracts the spatial distribution of oxide traps from the frequency dependence of transconductance, which is attributed to charge trapping as modulated by an ac gate voltage. The results from this method have been verified by the use of the multifrequency charge pumping (MFCP) technique. In fact, this method complements the MFCP technique in terms of the trap depth that each method is capable of probing. We will demonstrate the method with InP passivated InGaAs substrates, along with electrically stressed Si N-MOSFETs.

In Germanium-based metal-oxide-semiconductor field-effect transistors, a high-quality interfacial layer prior to high-? deposition is required to achieve low interface state densities and prevent Fermi level pinning. In this letter, the physical and electrical properties of a Ge/GeO2/Al2O3 gate stack are investigated. The GeO2 interlayer grown by radical oxidation and the formation of a germanate (GeAlOX) layer at the interface provide a stable high-quality passivation of the Ge channel. High carrier mobilities (235 cm2/V·s for electrons and 265 cm2/V·s for holes) are demonstrated for a relatively low 3.7-nm equivalent oxide thickness (EOT), enabling the realization of a high-performance CMOS technology with potential EOT scaling.