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This paper describes design methodologies for the optimal inductive peaking structures used for the 40-Gb/s serializing transmitter circuits presented in. The implemented transmitter had more than 400 on-chip inductors and transformers in order to achieve the bandwidth required for the 38.4-Gb/s operation demonstrated in a 0.13-μm CMOS process. A bridged T-coil network with inverted mutual coupling was found more effective than the conventional T-coil with sizeable driver-side capacitance. An iterative refinement procedure that directly optimizes the circuit's large-signal transient response at the presence of the inductor parasitics and device nonlinearities via HSPICE-ASITIC joint-simulation is described. The procedure resulted in more than 3 × improvement in bandwidth for the CML buffer, multiplexer, and latch circuits. It is shown that the area and the achievable bandwidth of the optimal inductive peaking structures will scale favorably with the CMOS technology trends.

A 20-GHz phase-locked loop with 4.9 ps/sub pp//0.65 ps/sub rms/ jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-/spl mu/m CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.

This paper describes the design and the implementation of a fully integrated 10 Gb Ethernet transceiver in a 0.13-/spl mu/m CMOS process using only a 1.2 V supply. A coarse control algorithm that combines a voltage range monitoring circuit with a frequency lock detector provides a robust operation against process, voltage, and temperature (PVT) variations for a VCO with a ring oscillator. With the use of a blind oversampling DPLL architecture, four channels of XAUI transceivers can share a single PLL, eliminating the clock synchronization problem between channels. Also, the total number of clock domains for the entire chip is reduced to three, making the integration of the XAUI with the 10G transceiver much simpler. The test chip consumes 898 mW from a 1.2 V supply.

This paper describes a technique for stabilizing the binary phase detector (PD) gain under various jitter conditions. A dead zone in the phase detector estimates the magnitude of high-frequency data jitter, and the resulting jitter information is used to control the charge-pump current. An alternating edge-sampling (AES) PD reduces hardware overhead by removing possible redundancies in previous dead-zone implementations. A series sense amplifier driven by a single-phase clock helps high-speed data sampling with increased data evaluation time. A dual path voltage-controlled oscillator incorporating dual-loop architecture enables wide-range operation of clock/data recovery circuits with low jitter. Fabricated in a 0.18-/spl mu/m CMOS process, a test transceiver operates from 2.5 to 11.5 Gb/s with a bit-error rate of less than 10/sup -12/ while consuming 540 mW from a 1.8-V supply.

This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval 3/spl times/-oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place the data-sampling clock exactly at the center of the data eye, responding to the shape and magnitude of jitter. A sampler with a pair of input-holding switches enables high-speed data sampling with reduced dynamic offset voltage. From the linearized model of the phase detector, the loop dynamics of the CDR are analyzed. Integrated in a single-chip transceiver with 0.25-/spl mu/m CMOS technology, the CDR operates at a data rate of 5 Gb/s. The CDR shows a bit error rate of less than 10/sup -13/ when the magnitude of data jitter reaches 60.5% of bit time.