26 results on '"Anami, K."'
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2. A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture
3. A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications
4. An asymmetric memory cell using a C-TFT for single-bit-line SRAM's
5. Response function of a stacked GSO(Ce) spectrometer to cosmic-rays
6. A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond
7. A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture
8. A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's
9. A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy
10. An 8 ns 4 Mb serial access memory
11. A 21-mW 4-Mb CMOS SRAM for battery operation
12. Variable bit organization as a new test function for standard memories
13. A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture
14. Simple noise model and low-noise data-output buffer for ultrahigh-speed memories
15. A 35 ns 16K NMOS static RAM
16. A latch-up-free CMOS RAM cell with well-source structure
17. Design consideration of a static memory cell
18. A macro analysis of soft errors in static RAMs
19. Improvement of soft-error rate in MOS SRAMs
20. 25-ns 256K×1/64K×4 CMOS SRAM's
21. A double-word-line structure in bipolar ECL random access memory
22. A 45-ns 256K CMOS static RAM with a tri-level word line
23. A fast 8K × 8 mixed CMOS static RAM
24. A 14-ns 1-Mbit CMOS SRAM with variable bit organization
25. A 920 gate DSA MOS masterslice
26. A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM
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