Search

The parallel combination of a switching and a linear amplifier in the supply modulator for RF power amplifiers (PAs) has the potential to enhance energy efficiency while achieving wider bandwidth and lower ripple output voltage. In this paper, a linear amplifier that features a buffered-switching Class-AB bias scheme is presented for the supply modulator in polar-transmitter structures achieving 500 MHz of small-signal 3-dB bandwidth at a 1.2-V supply. The linear amplifier absorbs and cancels up to 60 mA of ripple current from the switching amplifier. As such, the ripple in the output voltage of the hybrid linear-switching supply modulator is less than 7.5 mVpp. The switching amplifier provides most of the signal current for greatest efficiency owing to a proposed rail-to-rail current-sensing circuit. Current feedback in the switching amplifier achieves 1.68-MHz unity-gain bandwidth at 6-MHz switching frequency. Harmonic distortion in the output voltage of the supply modulator is below 40 dBc at 0.8 Vpp sinusoidal input up to 9 MHz. The peak efficiency is 87.7% for a 8.25- $\Omega $ load, while the maximum output power is 23.6 dBm for a 4.99- $\Omega $ load. The chip measures 1.35 mm2 in a 65-nm standard bulk CMOS process.

In this paper, a fully integrated digitally assisted low-dropout regulator (LDO) for a NAND flash memory system is proposed and verified using 500 nm I/O CMOS transistors. By combining an amplifier (AMP)-based LDO with a comparator (CMP)-based LDO, the proposed LDO achieves both fast load response in the transient state and accurate regulation in the steady state, which are advantages of the CMP-based LDO and AMP-based LDO, respectively. Moreover, loop frequency stability is satisfied in a wide range of load currents between 0 and 150 mA by using the simple structure of the $g_{m}$ -boost cell to insert an auxiliary path. For an input voltage range of 2.3–3 V and an output voltage of 2.1 V, the measured output droop is 225 mV for a 150 mA load step in the load transition time of 20 ns with the total bias current of $81\,\mu {\rm{A}}$ . The fabricated prototype chip occupies $160\,\times \,610\,\mu {\rm{m}}^{2}$ with an on-chip output capacitor of 2 nF.

A PRAM write driver with an auto-scaling overdrive method is presented. The proposed overdrive method significantly reduces the rise time of the cell-current pulse for bit-line parasitic components of 3 pF and 6 k $\Omega$ , and it lowers the complexity of the overdrive control using an adaptive charge amplification technique. A rise time of less than 15 ns is achieved and shortened up to 4.7 times, and the total write-throughput is increased. The rise time is reduced consistently for all levels of the target-current by the auto-scaling effect. Therefore, cell heating control becomes more linear in program-and-verify (PNV) operation. Due to its simple adding-on structure, it is easily compatible with a conventional write driver. A prototype chip was implemented using a 0.18- $\mu$ m CMOS process. It is also applicable to smaller-scale technology.

This paper presents a 65-nm CMOS low-dropout (LDO) regulator employing a super gain amplifier (SGA) and differential feed-forward noise cancellation to maximize the power supply rejection (PSR). The SGA in the error amplifier is augmented by a positive feedback current mirror, and this SGA boosts the loop gain through local negative feedback. With 1.2 V supply voltage, the LDO regulator has a 200 mV drop-out voltage and the ability to handle a maximum 25 mA load current. The measurement results show a -47 dB PSR ratio of up to 10 MHz and dc load regulation under 1 mV for full load current change.

124I has a complex decay scheme with high gamma energy and low positron abundance. In this study, comparative performance measurements of 124I were performed in terms of spatial resolution, sensitivity, and image quality. All measurements were performed using both 2D and 3D PET in both brain mode and whole body mode. The transverse and axial spatial resolutions at 1 cm were 5.56 and 6.07 mm for 124I, and were 4.58 and 4.77 mm and for 18F, respectively. Sensitivities were 0.5 kcps/MBq (2D) and 3.4 kcps/MBq (3D) for 124I, and 1.8 kcps/MBq (2D) and 9.8 kcps/MBq (3D) for 18F. The %contrast of 3D was higher than that of 2D in 124I. For 124I PET imaging, 3D acquisition with brain mode was highest achievable imaging acquisition mode with finer spatial resolution and higher contrast. This result will be useful for 124I PET imaging.

While the demand for micro-energy harvesters (μEHs) is increasing (for seamless energy source in applications such as wireless sensor node), two major problems still obstruct versatile use of them. The first problem is the self-startup capability. Because many wireless sensor nodes are likely to be located where human-maintenance is difficult, starting them up manually can be as difficult as replacing the battery. Its realization has been difficult because μEHs must be able to turn itself on without any stored energy. Some previous works have reported such a function: some needed high voltage [1] or vibration [2] and one used a transformer as a starter [3]. The other problem is the maximum power point tracking (MPPT) capability. Because it is known that MPPT algorithms usually require considerable power consumption [4], using them in μEHs is impractical. This paper suggests a new boost converter architecture and MPPT control method which can bring μEH into practical use.

This paper presents a method for estimating the signal frequency of sampled sinusoidal signals, which does not require any iteration for the frequency search. A noniterative method of frequency estimation was already developed by Zhang , where an analytical expression for the signal frequency is obtained using the differences between the neighboring input data. However, this method is very susceptible to additive noise. This paper extends the algorithm of Zhang to maintain the same signal-to-noise ratio as with the traditional four-parameter estimation method that requires iterations for the signal frequency search. Unfortunately, the proposed method is unable to estimate the accurate frequency in the case of an infinite number of data points when noises are added to the signal. From a noise analysis, it was found that the average frequency estimation error becomes zero when using a (2/3)π phase interval to calculate the signal difference. Numerical simulation results show that the frequency estimation error when Gaussian noise is added to the input data is about 13% higher than the square root of the Cramer-Rao bound. An additional 6% error is also added when the phase interval for frequency estimation deviates 10% from (2/3)π . Furthermore, it was found that the effect of harmonic components on the frequency estimation error can be minimized when the phase interval is close to (2/3)π, and the total number of data sample covers several signal periods or truncated close to an integer multiple of the signal period. As a result, the frequency estimation with the proposed method is more than 40 times more accurate than that with the IEEE-1057 method when the harmonic components are added to the input signal, which is confirmed by numerical simulations.