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We present a Verilog-A based compact model for the superconductor-insulator-superconductor (SIS) Josephson junction. The model can generate both hysteretic and non-hysteretic current-voltage ( I-V ) response for the SIS junctions utilizing the Stewart-McCumber parameter. We calibrate our model with different SIS samples and demonstrate accurate matching between the simulated and experimental results. We implement temperature effect on the energy gap and the critical current of the superconductor to explore the dynamic trends in device characteristics. We calculate the junction inductance and energy as functions of junction current and temperature. We simulate the read/write operations of an SIS junction based cryogenic memory cell to illustrate the usability of our model.

We propose SRAMs and DRAM with independent read–write paths employing phase transition material (PTM) in the read port to enable a more compact design compared to standardmultiport cells. Our technique employs 1) the orders of magnitude difference in the resistances of the insulating and metallic phases of the PTM and 2) regulated phase transitions to design a 7T single-ended SRAM, an 8T differential SRAM, and a 2T DRAM. Compared to previously proposed 8T SRAM, our 7T design achieves 9.1% less cell area and our 8T design achieves differential read without area penalty. We extensively analyze the material requirements for PTM to enable the proposed cell operation. We show that the read performance of the proposed 7T cell is only 5% worse than previously proposed standard 8T, while the proposed 8T design shows a 38% improvement. Similarly, our 2TDRAM cell achieves 20% less cell area than 3T DRAM, with less than 6% read time penalty. The benefits for all the designs come at no write overheads.

We analyze the augmentation of spin-transfer torque (STT) MRAM with electrically driven selective phase transition of a threshold switch (TS) to enhance the read operation. This paper provides a comprehensive discussion on necessary design considerations for TS augmented (TSA) MRAMs. We deduce constraints for read and write biasing that yields improved read operation of TSA MRAMs. We explain the dependence of read/write performance metrics on read/write biases and the properties (resistance and critical currents for transitions) of the TS. With proper device-circuit optimization, TSA MRAM shows up to 70% larger sense margin, ~27% higher data stability with ~40% less power for read operation compared to STT MRAM (in nominal condition). We evaluate the impact of variation on TSA MRAM through Monte Carlo simulations. We report that even with variation induced spread in the distribution of bit-line voltages, TSA MRAM provides $\sim 1.7\times $ larger voltage differential between parallel and antiparallel states. For the write operation, the TSA MRAM consumes ~10% less average power and demands only ~5% more write time extension than the STT MRAM to achieve the same level of variation tolerance.

This brief exploits the fusion of low-power logic and nonvolatile memory inside the emerging ferroelectric FETs (FeFETs) and proposes a new nonvolatile D flip-flop (nvDFF) through the device-circuit co-design. Compared with existing FeFET-based nvDFFs with on-demand control of backup and restore (B&R), the area overhead is lowered by half, and the routing cost is reduced with embedded backup control into the supply voltage. Circuit simulations show below 5% energy-delay overhead in the normal mode and femtojoule B&R energy. This new nvDFF promises area- and energy-efficient nonvolatile computing for power-gating and energy-harvesting applications.

Nonvolatile computing has been proven to be effective in dealing with power supply outages for on-chip check-pointing in emerging energy-harvesting Internet-of-Things applications. It also plays an important role in power-gating to cut off leakage power for higher energy efficiency. However, existing on-chip state backup solutions for D flip–flop (DFF) have a bottleneck of significant energy and/or latency penalties which limit the overall energy efficiency and computing progress. Meanwhile, these solutions rely on external control that limits compatibility and increases system complexity. This paper proposes an approach to fundamentally advancing the nonvolatile computing paradigm by intrinsically nonvolatile area-efficient latches and flip–flops designs using negative capacitance FET. These designs consume fJ-level energy and ns-level intrinsic latency for a backup plus restore operation, e.g., 2.4 fJ in energy and 1.1 ns in time for one proposed nonvolatile DFF with a supply power of 0.80 V.

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ${I}_{D}$ – ${V}_{G}$ hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing ${R}_{\text {DS}}$ ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high ${R}_{\text {DS}}$ ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications.

Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer ( $T_{\textsf {FE}})$ is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of $T_{\textsf {FE}}$ on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing $T_{\textsf {FE}}$ yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as $T_{\textsf {FE}}$ is increased. Depending on the attributes of the underlying transistor, increasing $T_{\textsf {FE}}$ beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of $T_{\textsf {FE}}$ on the circuit energy–delay. Our analysis shows that for high $T_{\textsf {FE}}$ , the delay of the circuit may increase with an increase in supply voltage. However, for voltages

Hybrid-phase-transition FETs (Hyper-FETs) are recently proposed steep switching devices that utilize the phase transition materials (PTM) to achieve a boost in the ratio of ON ( ${I}_{{{\mathrm {ON}}}})$ and OFF currents ( ${I}_{{{\mathrm {OFF}}}})$ . Prototypical demonstrations of the Hyper-FET have shown performance improvement in comparison with conventional transistors, which motivates the evaluation of its device-circuit design space. In part I, we analyze the device aspects establishing the effects of the resistivity and phase transition thresholds of the PTM on the characteristics of Hyper-FETs. Our analysis shows that the ratio of insulating and metallic state resistivity ( $\rho _{\mathrm {INS}}$ and $\rho _{\mathrm {MET},}$ respectively) of the PTM needs to be higher than the ${I}_{{{\mathrm {ON}}}} /I_{{{\mathrm {OFF}}}}$ of its host transistor to achieve performance improvement in Hyper-FET. For a host transistor with $I_{{{\mathrm {OFF}}}} = 0.051\mu \text{A}/\mu \text{m}$ and ${I}_{{{\mathrm {ON}}}} = 191.5\mu \text{A}/\mu \text{m}$ , $\rho _{\mathrm {MET}} .cm and $\sim 7.5~\Omega $ .cm $ .cm is required to achieve proper device functionality with a boost in ${I}_{{{\mathrm {ON}}}}/{I}_{{{\mathrm {OFF}}}}$ . Additionally, we establish the ranges of phase transition thresholds that yield proper functionality of the Hyper-FETs considering different ${I}_{{{\mathrm {OFF}}}}$ targets. The methodology of choosing appropriate PTM geometry to achieve the target device characteristics is also described. We show that with proper design, Hyper-FETs achieve 94% larger ${I}_{{{\mathrm {ON}}}}$ at iso- ${I}_{{{\mathrm {OFF}}}}$ compared with a FinFET. We examine the circuit design aspects of Hyper-FET in part II.

We present an extensive analysis of functional-oxide based selector devices for cross-point memories from the perspectives of materials through arrays. We describe the design constraints required for proper functionality of a cross-point array and translate these constraints to figures of merit for the selector materials. The proposed figures of merit, related to the resistivities of the functional oxide in the metallic and insulating states and the critical current densities for insulator-metal transitions, determine whether or not a functional oxide is suitable to be employed as a selector for a memory technology. Our analysis shows the importance of co-optimizing the selector length with the read/write voltages and establishes the range of these parameters for proper functionality. We also perform an extensive material space analysis for the selector, relating the selector properties to the achievable array metrics. For instance, we show that optimized memory array with single crystal VO $_{\mathrm {{2}}}$ based selector and spin-memory element achieves $\sim 25\mu \text {A}$ sense margin with ~ 30% read disturb margin and 40ns write time. The leakage in the half-accessed cell can be as low as $15\mu \text {W}$ . The design principles established in this work will provide guidelines for future exploration of functional oxides for selector applications as well as for the optimization of cross-point arrays.

We propose a novel static random access memory (SRAM) cell employing correlated material (CM) films in conjunction with the transistors to achieve higher read stability, write ability, and energy efficiency. The design of the proposed SRAM cell utilizes orders of magnitude difference in the resistance of the insulating and metallic phases of the CM to mitigate the design conflicts. By appropriately controlling the phase transitions in the CM films during SRAM operation through device–circuit codesign, we achieve 30% higher read static noise margin and 36% increase in the write margin over standard SRAM. The proposed design also leads to a 50% reduction in the leakage current due to high insulating state of the CM. This is achieved at 28% read time penalty. We also discuss the layout implications of our technique and present techniques to sustain no area overhead.

We present a hybrid multiplexing (HYM) scheme for MRAMs with separate read-write paths, employing different bit-cell selection methods during read and write based on their suitability for data sensing and switching operations. The proposed technique allows the sharing of the read access transistor among the cells belonging to the same word, leading to area savings and enhancement in distinguishability. Furthermore, by employing dummy bits in an array and setting their values according to the process corner, the spread of the read current due to global variations can be tightened. We apply our technique on MRAM with spin Hall effect-based write and show that the HYM achieves 20% to 25% area reduction along with 2.4X improvement in cell TMR, 25% to 38% lower write power, and upto 50% increase in the read disturb margin compared to the standard multiplexing. The spread of the read current reduces by 38% to 53% by employing the dummy bits.