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Firmware functional validation suffers from a series of performance limitations in practice, which in turn heavily relies on manual effort and becomes a major bottleneck of product time cycle. The requirement of repetitive run-time firmware execution for the validation environment demands novel techniques to accelerate the validation process. We propose an online firmware functional validation scheme utilizing the colored Petri net (CPN) model which can be generated automatically from the firmware source code. With simulation runs on the generated CPN models at run-time, the firmware execution path is presented and, if an error occurs, the location of error can be identified. An integrated validation tool has been designed and implemented to show the proposed validation methodology’s potential and effectiveness. This tool is used in the validation of the universal serial bus (USB) initialization in unified extensible firmware interface (UEFI).

Power gating is commonly used to reduce leakage current in SRAM memories; leakage current has a large impact on SRAM energy consumption. We first focus on power gating FinFET SRAMs and then evaluate three techniques to reduce the leakage power and energy-delay product (EDP) of six- and eight-transistor (6T, 8T) FinFET SRAM cells. We compare the EDP savings obtained using: 1) power gating FinFETs; 2) near-threshold operation at $V_{\mathrm{ DD}}=0.6$ V instead of the nominal $V_{\mathrm{ DD}}=1$ V; and 3) alternative SRAM cells with shorted gate (SG) and low power (LP) configured FinFETs; LP-configuration reverse-biases a FinFET’s back gate and reduces leakage current by up to 97%. SRAM cells with higher leakage benefit the most from power gating since they see the largest reductions in leakage current. Sharing power gating transistors among multiple SRAM cells can lead to more leakage current savings, but causes slower read and write speeds which can diminish their effectiveness. Alternative SRAM cells with lower leakage benefit the most from near-threshold operation to further reduce leakage current. Near-threshold operation and/or power gating reduces the 6T SG FinFET SRAM scheme’s EDP slightly more than using the 8T SG FinFET SRAM scheme, but using an LP 8T SRAM scheme, such as LP_INV1.2, with near-threshold operation is more effective than power gating and provides the largest reductions in EDP. The design techniques recommended by this brief can enable longer battery life for small sensor systems and thus greater reliability for Internet-of-Things (IoT) devices.

The International Midwest Symposium on Circuits and Systems is the oldest Circuits and Systems Symposium sponsored by the IEEE CAS Society. This conference contributes to its strong history by reporting the latest research results and innovations in the field of circuits and systems through Distinguished Speakers featuring the newest innovations relevant to this field and shedding light on its evolution toward breaching the gaps among technologies. The 62nd International Midwest Symposium on Circuits and Systems (MWSCAS-2019) was held in Dallas, TX, USA, and received 405 article submissions. Among all the accepted contributions, a subset of these articles were selected and invited for this Special Issue. The invited articles went through a peer-review process consisting of the world-recognized reviewers in related fields. A brief description of the selected articles are as follows.

In this study, we report an in-depth study of power supply reduction toward near threshold for an eight-transistor carbon nanotube (CNT) field-effect transistors SRAM cell. Near-threshold voltage has an impact on delays, energy, energy-delay product, leakage current, and static noise margin. In addition, we have incorporated a removed metallic CNT approach to deal with nonsemiconductor CNTs. Monte Carlo simulations at Vdd (power supply voltage) of 0.4 V have shown that 97.24% of the cells are functional after removing the metallic CNTs. The power saving is over 5× and the average delay is increased by 3.5× as compared to a typical Vdd of 0.9 V. To further improve yield and performance, a word-line boosting technique is explored. Read and write word lines are boosted with additional 100 mV; this in turn effectively eliminates all the write failures at the 0.4 V level and reduces read and write delays. Comparing boosted and nonboosted cells with Vdd = 0.4 V, the boosted cell has write and read delays that are faster by 3.8× and 1.7×, respectively. This cell's energy increases by less than 4% per-access in the worst case. The cell with Vdd of 0.4 V with boosted word-lines achieves the lowest energy-delay product of all the cases considered in this study, which is 52.3% and 56.9% lower than that of a boosted and nonboosted cell with Vdd of 0.9 V, respectively.

A study of an eight-transistor static random access memory (SRAM) cell and its implementation in carbon nanotube FET (CNTFET) technology are presented. Simulations of the CNTFET SRAM cell design, using a CNT SPICE model, have shown advantages over the CMOS cell in terms of static power, dynamic power, and noise margin. However, current CNT synthesis processes grow metallic CNTs alongside semiconductor CNTs. This in turn greatly degrades the performance and functionality of SRAM cells. In this paper, we present and compare two approaches to overcome the presence of metallic CNTs. The first approach tolerates metallic CNTs and uses a series of uncorrelated CNTs to form a transistor; this provides tolerance to metallic CNTs. The second approach uses an M × N array of uncorrelated CNTs to form a CNTFET and requires technologies capable of removing metallic CNTs. Both approaches have similar static noise margin. The second approach (removed metallic CNTs) consumes 1.45× more static power; on the other hand, its CNT count and write delay are reduced to 35.6% and 10.9% of the metallic tolerant approach, respectively. The realization of large memory modules in the presence of faulty SRAM cells can be achieved by having memory modules with as few as two spare columns.

In the presence of radiation, particle strikes can cause temporary signal errors in ICs. Particle strikes that directly affect memory are known as single event upsets (SEUs), while strikes that affect combinational logic and spread to memory are called single event transients (SETs). This paper focuses on SEU and SET-tolerant approaches to constructing pipeline latches and flip-flops. Level-sensitive latches, edge-triggered master-slave flip-flops, and pulse-triggered flip-flops comprise the pipeline memory classes considered in this paper. TPDICE basic cells are utilized to achieve fault-tolerance and transient bypass capability. A number of single-ended and differential structures are presented and evaluated with respect to performance, energy consumption, and complexity. In addition, the SEU and SET tolerance of these structures is demonstrated. All evaluations are based off simulations performed in 90 nm CMOS. Accompanying the above evaluations, this paper also addresses concerns of multiple bit upset (MBU) affecting these designs at the 90 nm technology node. Novel hardened-by-design techniques are introduced to address these concerns, and their effectiveness is quantified.

Two novel address decoder schemes using selective precharging are presented and analyzed in this paper. These schemes, the AND-NOR and sense amplifier (sense-amp) decoders, are compared to the NOR decoder using 90-nm CMOS technology. The sense-amp decoder dissipates between 29.5% and 50.1% and the AND-NOR decoder dissipates between 73.7% and 104.4% of the energy dissipated by the NOR decoder. The delay of the Sense-Amp decoder is 69.2% and the delay of the AND-NOR decoder is 80.8% of the nor decoder delay.

Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable architecture that combines the advantages of both approaches. Modules such as multipliers and adders are mapped onto blocks of 4-bit cells. Each cell contains a matrix of lookup tables that either implement mathematics functions or a random-access memory. A hierarchical interconnection network supports data transfer within and between modules. We have created software tools that allow users to map algorithms onto the reconfigurable platform. This paper analyzes the implementation of several common benchmarks, ranging from floating-point arithmetic to a radix-4 fast Fourier transform. The results are compared to contemporary DSP hardware.

Scalable high-performance routers and switches are required to provide a larger number of ports, higher throughput, and good reliability. Most of today's routers and switches are implemented using single crossbar as the switched fabric. The single crossbar complexity increases at O(N2) in terms of crosspoint number, which might become unacceptable for scalability as the port number (N) increases. A delta class self-routing multistage interconnection network (MIN) with the complexity of O(N times log2N) has been widely used in the asynchronous transfer mode switches. However, the reduction of the crosspoint number results in considerable internal blocking. A number of scalable methods have been proposed to solve this problem. One of them uses more stages with recirculation architecture to reroute the deflected packets, which greatly increase the latency. In this paper, we propose an interleaved multistage switching fabrics architecture and assess its throughput with an analytical model and simulations. We compare this novel scheme with some previous parallel architectures and show its benefits. From extensive simulations under different traffic patterns and fault models, our interleaved architecture achieves better performance than its counterpart of single panel fabric. Our interleaved scheme achieves speedups (over the single panel fabric) of 3.4 and 2.25 under uniform and hot-spot traffic patterns, respectively, at maximum load (p = 1). Moreover, the interleaved fabrics show great tolerance against internal hardware failures.

Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable architectures for digital signal processing (DSP) use coarse-grain cells that perform 16-b or 32-b operations. A third alternative is to use medium-grain cells with a word length of 4 or 8 b. This approach combines high flexibility with inherent support for binary arithmetic such as multiplication. This paper presents two medium-grain cells for reconfigurable DSP hardware. Both cells contain an array of small lookup tables, or ldquoelementsrdquo, that can assume two structures. In memory mode, the elements act as a random-access memory. In mathematics mode, the elements implement 4-b arithmetic operations. The first design uses a matrix of 4 times 4 elements and operates in bit-parallel fashion. The second design uses an array of five elements and computes arithmetic functions in bit-serial fashion. Layout simulations in 180-nm CMOS indicate that the parallel cell operates at 267 MHz, whereas the serial cell runs at 167 MHz. However, the parallel design requires over twice the area. The proposed medium-grain cells provide the performance and flexibility needed to implement DSP. To evaluate the designs, the paper estimates the execution time and resource utilization for common benchmarks such as the fast Fourier transform. The architecture model used in this analysis combines the cells with a pipelined hierarchical interconnection network. The end results show great promise compared to other devices, including field-programmable gate arrays.

In the presence of radiation, particle strikes can cause temporary signal errors in ICs. Particle strikes that directly affect memory are known as single event upsets (SEUs), while strikes that affect combinational logic and spread to memory are called single event transients (SETs). In this paper, we propose two novel approaches to hardening integrated circuits against SEUs and SETs. The proposed approaches are fully-differential dual-interlocked storage cell (DICE) and triple path DICE (TPDICE). The fully-differential DICE and TPDICE approaches are compared against two existing approaches, which are triple modular redundancy (TMR) and basic SET-tolerant DICE. All approaches except for the basic SET-tolerant DICE scheme share a common theme, which is the ability to bypass SEUs and SETs. This is critical for performance, as it allows the system to proceed with subsequent operations while a cell is recovering from the effects of a particle strike. SET pulse widths can be substantial (up to 2 ns), and so high-performance systems cannot afford to pause operations while these pulses are present. The minimum clock periods obtained for the basic SET-tolerant approach were 515 ps with no SET, and 1310 ps with a 500 ps SET (in 0.18 /spl mu/m CMOS). In contrast, the clock periods for the bypass-capable approaches with no SET/500 ps SET were 628/749 ps for TMR, 348/480 ps for fully-differential DICE, and 434/552 ps for TPDICE. Among the approaches that bypass transient pulses, TPDICE is the most balanced. TMR suffers from overhead due to its need for external voting circuitry. In addition to this, fully-differential DICE cannot be used with combinational logic, while TPDICE can.

A novel mesochronous pipelining scheme is described in this paper. In this scheme, data and clock travel together. At any given time a pipeline stage could be operating on more than one data wave. The clock period in the proposed pipeline scheme is determined by the pipeline stage with largest difference between its minimum and maximum delays. This is a significant performance gain compared to conventional pipeline scheme where clock period is determined by the stage with the largest delay. A detailed analysis of the clock period constraints is provided to show the performance gains and Speedup of mesochronous pipelining over other pipelining schemes. Also, the number of pipeline stages and pipeline registers is small. The clock distribution scheme is simple in the mesochronous pipeline architecture. An 8 /spl times/ 8-bit carry-save adder multiplier has been implemented in mesochronous pipeline architecture using modest TSMC 180-nm (drawn length 200 nm) CMOS technology. The multiplier architecture and simulation results are described in detail in this paper. The pipelined multiplier is able to operate on a clock period of 350 ps (2.86 GHz). This is a Speedup of 1.7 times over conventional pipeline scheme, with fewer pipeline stages and pipeline registers.

The content addressable memory (CAM) is a memory in which data can be accessed on the basis of contents rather than by specifying physical address. In the paper, five novel dynamic ternary CAM cells with decoupled match lines are presented. A ternary CAM cell is capable of storing and matching three values: zero (0), one (1), and don't care (X). The proposed dynamic CAM (DCAM) cells range in the number of transistors from 6 n-type transistors up to 10.5 n- and p-type transistors (one transistor is shared between two cells). The cells are capable of fast match and read operations enhancing the performance of the memory system. Using a 0.25-/spl mu/m CMOS technology, simulations of the proposed CAM cells were performed to compare their performance. With this technology, the shortest match delay is 89.7 ps for the 7.5 DCAM cell. A complete characterization of the five cells is provided in this paper. These results show that the novel CAM cells outperform existing cells. The compact size and low power dissipation of these ternary CAM cells make them suitable for many applications such as routers, database, and associative cache memories.

Crossbar switch is a key component of communication switches used in networks. Allocation of resources has a direct impact on packet transmission. A poor allocation results in long transmission delays. Hence, switches must include an arbiter that efficiently allocates the crossbar's resources. In this brief, a novel VLSI CMOS implementation of a high performance wrapped wave front arbitration (WWFA) for crossbar switches is described. Arbitration time is one of the critical factors that affect network performance. WWFA requires a two-dimensional arbitration that incorporates a rotating priority to provide fair arbitration. In this brief, we describe the design and implementation of this arbiter. The arbiter is capable of performing an arbitration in 1.15 ns using 0.5-/spl mu/m technology, for a 4 /spl times/ 4 crossbar. We also include the description of interface and crosspoint (CP) control circuitry, i.e., request-acknowledge circuit and CP controller circuit respectively.

In this paper, a novel hybrid wave pipelined bit-pattern associative router (BPAR) is presented. A router is an important component in communication network systems. The BPAR allows for flexibility and can accommodate a large number of routing algorithms. In this study, a hybrid wave pipelined approach has been proposed and implemented. Hybrid wave pipelining allows for the reduction of the delay difference between the maximum and minimum delays by narrowing the gap between each stage of the system. This approach yields narrow "computing cones" that could allow faster clocks to be run. This is the first study in wave pipelining that deals with a system that has substantially different pipeline stages. The BPAR has three stages: condition match, selection function, and port assignment. In each stage, data delay paths are tightly controlled in order to optimize the proper propagation of signals. Internal control signals are generated to ensure that data propagates between stages in a proper fashion. Results from our study show that using a hybrid wave pipelining significantly reduces the clock period. The hybrid wave pipelined system described in this paper has been fabricated using a 0.5-/spl mu/m technology.

In this brief, we introduce a priority encoder that uses a novel priority lookahead (PL) scheme to reduce delays associated with priority propagation. Two priority encoder approaches are presented, one without and the other with a PL scheme. For an N-bit encoder, the circuit with the PL scheme requires about 0.1 more transistors than the circuit without the scheme. However, a 32-bit very large scale integration (VLSI) encoder with the PL scheme is about 2.5 times faster than the other encoder. The worst case operation delay is 4.4 ns for this lookahead encoder using a 1 /spl mu/m scalable complementary metal-oxide-semiconductor (CMOS) technology.

A VLSI implementation of a programmable pipelined router scheme for parallel machine interconnection networks is presented in this paper. The implementation is based on a dynamic content-addressable memory (DCAM) that supports unique bit masking per entry. The number of required DCAM entries is extremely small; it is of the same order as the node degree (output ports). This, in turn, makes it possible to implement a dynamic content-addressable memory in order to reduce the physical size of the system. A DCAM is implemented with only six and a half transistors (one transistor is shared by two cells). We have provided circuitry and arranged timing to achieve refreshing of the stored data in a hidden fashion. In addition to the DCAM, we have incorporated a fast priority scheme that allows only one entry to he selected. The router executes routing algorithms in 1.5 clock cycles, this being the fastest approach for flexible routers. The prototype router has 24 entries, and is able to sustain a throughput of one routing decision per cycle.

A programmable associative approach to execute implicit routing algorithms is presented. Algorithms are mapped onto a set of bit-patterns that are matched in parallel. We have studied and mapped a large number of routing algorithms for a wide range of interconnection network topologies. Here we report three cases that illustrate the capabilities of the router scheme. For the studied topologies, the number of required bit-patterns is of the same order as the topology degree. The proposed approach is one of the fastest routers and requires a very small amount of hardware.

A piecewise second order approximation scheme is proposed for computing the sigmoid function. The scheme provides high performance with low implementation cost; thus, it is suitable for hardwired cost effective neural emulators. It is shown that an implementation of the sigmoid generator outperforms, in both precision and speed, existing schemes using a bit serial pipelined implementation. The proposed generator requires one multiplication, no look-up table and no addition. It has been estimated that the sigmoid output is generated with a maximum computation delay of 21 bit serial machine cycles representing a speedup of 1.57 to 2.23 over other proposals.

The use of a molecular beam epitaxy engineered InGaAs/GaAs semiconductor structure to quasioptically modulate a millimeter wave Gaussian beam using an optical control signal has been demonstrated. The RF transmission is modulated spatially by the optically generated excess carrier density. Low optical intensities are sufficient due to the long recombination lifetime achieved in the nipi-doped structure used. A modulation depth of more than 15 dB in transmission mode has been obtained at 100 GHz. Modulation has been measured up to 5 THz using a Fourier transform spectrometer. >