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Recent translational efforts in brain-machine interfaces (BMI) are demonstrating the potential to help people with neurological disorders. The current trend in BMI technology is to increase the number of recording channels to the thousands, resulting in the generation of vast amounts of raw data. This in turn places high bandwidth requirements for data transmission, which increases power consumption and thermal dissipation of implanted systems. On-implant compression and/or feature extraction are therefore becoming essential to limiting this increase in bandwidth, but add further power constraints – the power required for data reduction must remain less than the power saved through bandwidth reduction. Spike detection is a common feature extraction technique used for intracortical BMIs. In this paper, we develop a novel firing-rate-based spike detection algorithm that requires no external training and is hardware efficient and therefore ideally suited for real-time applications. Key performance and implementation metrics such as detection accuracy, adaptability in chronic deployment, power consumption, area utilization, and channel scalability are benchmarked against existing methods using various datasets. The algorithm is first validated using a reconfigurable hardware (FPGA) platform and then ported to a digital ASIC implementation in both 65 nm and 0.18MU m CMOS technologies. The 128-channel ASIC design implemented in a 65 nm CMOS technology occupies 0.096 mm2 silicon area and consumes 4.86MU W from a 1.2 V power supply. The adaptive algorithm achieves a 96% spike detection accuracy on a commonly used synthetic dataset, without the need for any prior training.

Chronic in-vivo neurophysiology experiments require highly miniaturized, remotely powered multi-channel neural interfaces which are currently lacking in power or flexibility post implantation. In this article, to resolve this problem we present the SenseBack system, a post-implantation reprogrammable wireless 32-channel bidirectional neural interfacing that can enable chronic peripheral electrophysiology experiments in freely behaving small animals. The large number of channels for a peripheral neural interface, coupled with fully implantable hardware and complete software flexibility enable complex in-vivo studies where the system can adapt to evolving study needs as they arise. In complementary ex-vivo and in-vivo preparations, we demonstrate that this system can record neural signals and perform high-voltage, bipolar stimulation on any channel. In addition, we demonstrate transcutaneous power delivery and Bluetooth 5 data communication with a PC. The SenseBack system is capable of stimulation on any channel with p20 V of compliance and up to 315 μA of current, and highly configurable recording with per-channel adjustable gain and filtering with 8 sets of 10-bit ADCs to sample data at 20 kHz for each channel. To the best of our knowledge this is the first such implantable research platform offering this level of performance and flexibility post-implantation (including complete reprogramming even after encapsulation) for small animal electrophysiology. Here we present initial acute trials, demonstrations and progress towards a system that we expect to enable a wide range of electrophysiology experiments in freely behaving animals.

Coherent ultra-wideband (UWB) radar-on-chip technology shows great promise for developing portable and low-cost medical imaging and monitoring devices. Particularly monitoring the mechanical functioning of the cardiovascular system is of interest, due to the ability of radar systems to track sub-mm motion inside the body at a high speed. For imaging applications, UWB radar systems are required, but there are still significant challenges with in-body sensing using low-power microwave equipment and wideband signals. Recently it was shown for the first time, on a single subject, that the arterial pulse wave can be measured at various locations in the body, using coherent UWB radar-on-chip technology. The current work provides more substantial evidence, in the form of new measurements and improved methods, to demonstrate that cardiovascular dynamics can be measured using radar-on-chip. Results across four participants were found to be robust and repeatable. Cardiovascular signals were recorded using radar-on-chip systems and electrocardiography (ECG). Through ECG-aligned averaging, the arterial pulse wave could be measured at a number of locations in the body. Pulse arrival time could be determined with high precision, and blood pressure pulse wave propagation through different arteries was demonstrated. In addition, cardiac dynamics were measured from the chest. This work serves as a first step in developing a portable and low-cost device for long-term monitoring of the cardiovascular system, and provides the fundamentals necessary for developing UWB radar-on-chip imaging systems.

This paper investigates continuous-time (CT) signal acquisition as an activity-dependent and nonuniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by nonuniform quantisation to commonly recorded biological signal fragments allowing a compression ratio of $\approx$ 5 and 26 when applied to electrocardiogram and extracellular action potential signals, respectively. We describe several desirable properties of CT sampling, including bandwidth reduction, elimination/reduction of quantisation error, and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT analogue-to-digital converter that has been optimized for the acquisition of neural signals. This has been implemented in a commercially available 0.35 $\mu \text{m}$ CMOS technology occupying a compact footprint of 0.12 mm2. Silicon verified measurements demonstrate an 8-bit resolution and a 4 kHz bandwidth with static power consumption of 3.75 $\mu$ W from a 1.5 V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39 pJ energy per conversion.

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth- order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure- of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst addition- ally offering direct integration with digital systems.

Comunicación presentada al "ISCAS 2011" celebrado en Rio de Janeiro (Brasil) del 15 al 18 de Mayo del 2011.-- et al., People rarely put in their papers the things that didn't work, the mistakes they made, and how they found out what went wrong. Such confessions can help others learn how to avoid similar mistakes. Twenty-six confessions were collected to form the bulk of this paper. Themes that arise are errors that result from not understanding the limitations of simulation tools in modeling physical reality, chip verification errors that result from lack of clear communication between designers, and projects that are considered in their own isolated environment of technical challenges rather than the broader context of their environment or application.