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2. Heavy ion testing with iron at 1 GeV/amu

3. Non-TMR SEU-hardening techniques for SiGe HBT shift registers and clock buffers

4. Estimation of heavy-ion LET thresholds in advanced SOI IC technologies from two-photon absorption laser measurements

5. Single-event upsets and multiple-bit upsets on a 45 nm SOI SRAM

6. Junction isolation single event radiation hardening of a 200 GHz SiGE: C HBT technology without deep trench isolation

7. Re-examining TID hardness assurance test protocols for SiGE HBTs

8. Impact of low-energy proton induced upsets on test methods and rate predictions

9. Heavy ion microbeam- and broadbeam-induced transients in SiGe HBTs

10. Design implications of single event transients in a commercial 45 nm SOI device technology

11. Laser-induced current transients in silicon-germanium HBTs

12. Device-orientation effects on multiple-bit upset in 65 nm SRAMs

13. Single event upset mechanisms for low-energy-deposition events in SiGe HBTs

14. The effects of angle of incidence and temperature on latchup in 65 nm technology

15. A generalized SiGe HBT single-event effects model for on-orbit event rate calculations

16. Substrate engineering concepts to mitigate charge collection in deep trench isolation technologies

17. Multiple-bit upset in 130 nm CMOS technology

18. An investigation of dose rate and source dependent effects in 200 GHz SiGe HBTs

19. Laser-induced current transients in strained-Si diodes

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