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Any real architecture designed only in the CNFET technology as a hopeful substitution of the silicon CMOSFET has not been developed because of shortage of self-assembly CNFET technology for designing complex CNFET structures. Therefore, for designing the real architecture in the current self-assembly CNFET technology, the development of a simple CNFET circuit structure forming all the digital function is required. This paper proposes a simple CNFET circuit structure using back-gate voltages to design the real digital architecture and to overcome the high fabrication cost of CNFETs and manufacturing variability and imperfection of CNFET technology. The function of the proposed CNFET cell is determined by the back-gate voltages, and the determined function is the same as NAND or NOR gate function. The simulation results present that the propagation delay time of the ISCAS85 circuits in a 32nm Stanford CNFET technology deploying the proposed CNFET cells is reduced by over 42% compared to the conventional CNFET cell in ultra-low voltage (0.4V).

As technology scales down, it has become one of the most critical issues in aging-tolerant nanoscale MOSFET circuit design to monitor the performance degradation of the circuits under aging stress conditions such as Negative-Bias-Temperature Instability (NBTI) and Hot-Carrier-Injection (HCI). Hence, this paper proposes a novel on-chip circuit to measure the delay degradation of stressed MOSFET digital circuits and digitalize the degradation for aging compensation. A 0.11μm CMOS technology has been used to implement and evaluate the proposed circuits.