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Driven by flexibility, performance and cost constraints of demanding modern applications, heterogeneous System-on-Chip (SoC) is the dominant design paradigm in the embedded system computing domain. SoC architecture and heterogeneity clearly provide a wider power/performance scaling, combining high performance and power efficient general-purpose cores along with massively parallel many-core-based accelerators. Besides the complex hardware, generally these kinds of platforms host also an advanced software ecosystem, composed by an operating system, several communication protocol stacks, and various computational demanding user applications. The necessity to efficiently cope with the hugeHW/SW design space provided by this scenario makes clearly full-system simulator one of the most important design tools. We present in this paper a new emulation framework, called Virtual SoC, targeting the full-system simulation of massively parallel heterogeneous SoCs.

A shared-L1 cache architecture is proposed for tightly coupled processor clusters. Sharing an L1 tightly coupled data memory (TCDM) among a significant (up to 16) number of processors is challenging in terms of speed. Sharing L1 cache is even more challenging, since operation is more complex, as it eases programming. The feasibility in terms of performance of shared TCDM was shown in ST Microelectronics platform 2012, but the performance cost of supporting shared L1 cache remains to be proven. In this paper we show that replacing TCDM with a multi-banked shared-L1 cache imposes limited speed overhead. Of course, it comes at the cost of area and power. We explore the shared L1 cache architecture in terms of number of processing elements (PEs) and cache banks. Experimental results show that our multi-banked shared-L1 cache can operate with almost the same frequency as that of related TCDM architecture if the cache controller uses a cache line of 4 words. Results also show that, the area overhead with respect to TCDM is less than 18% for a cluster containing 16 Leon3 processors and 32 cache banks. We also show that the overhead on MIPS/Watt and MIPS/mm2 is from 5% to 30% depending on the size of processor in the cluster for a 16×32 configuration (16 cores and 32 cache/memory banks).

Air quality monitoring in indoor environments is of great significance for comfort and health, especially nowadays that people spend more than 80% of the day indoor. We propose a flexible wireless system able to detect polluted air and dangerous situations in a complex and large environment. It is important for ambient intelligent systems to be unobtrusive and to optimize the power consumption of the platforms in order to be able to live on batteries for several years. We present a system with aggressive energy management that involves three levels: sensor level, node level and network level. The sensor board we designed is a wireless sensor network (WSN) node, with very low sleep current consumption (only 8 µA). It contains two modalities — a gas sensor and a Pyroelectric InfraRed (PIR) sensor. The network is multimodal: it uses information from the PIR sensor and neighbor nodes to detect the presence of people and to modulate the duty cycle of the node and the Metal Oxide Semiconductor (MOX) gas sensor. In this way we reduce the nodes' activity and energy requirements, providing a reliable service at the same time. We simulate the benefits of the context-aware adaptive duty-cycling of the gas sensor activity and we demonstrate a significant lifetime extension compared to the continuously driven gas sensor (several years vs. several days).

The reliability of networks-on-chip (NoC) is threatened by low yield and device wearout in aggressively scaled technology nodes. We propose ReliNoC, a network-on-chip architecture which can withstand failures, while maintaining not only basic connectivity, but also quality-of-service support based on packet priorities. Our network leverages a dual physical channel switch architecture which removes the control overhead of virtual channels (VCs) and utilizes the inherent redundancy within the 2-channel switch to provide spares for faulty elements. Experimental results show that ReliNoC provides 1.5 to 3 times better network physical connectivity in presence of several faults, and reduces the latency of both high and low priority traffic by 30 to 50%, compared to a traditional VC architecture. Moreover, it can tolerate up to 50 faults within an 8×8 mesh at only 10 and 40% latency overhead on control and data packets for PARSEC traces [24]. Synthesis results show that our reliable architecture incurs only 13% area overhead on the baseline 2-channel switch.

This paper reports the characterization and test of an embedded implementation of the k-Nearest Neighbor (kNN) classifier in a resource constrained device applied to a seat to capture user postures and combine them with contextual information about the user. The embedded platform is a wearable multi-sensor device based on the 32 bit ARM Cortex M3 architecture, capable of data processing (sampling, windowing, filtering, Fast Fourier Transform) from 9 different sensors. The system, applied to the seat, identifies 6 different user postures - adopted while she/he is working on the desk - and fuses the result with the information available from other sensors worn by the user, collecting information about her/his activities and physiological state. The kNN classifier is evaluated in terms of required computational power and latency. 7 users have been monitored along 3 days. The posture recognition accuracy reaches 93.7%, it requires 9KB of memory and introduces a latency of 950usec, satisfying strict real-time requirements.

The impact of variability on sub-45nm CMOS multimedia platforms makes hard to provide application QoS guarantees, as the speed variations across the cores may cause sub-optimal and sample-dependent utilization of the available resources and energy budget. These effects can be compensated by an efficient allocation of the workload at run-time. In the context of multimedia applications, a critical objective is to compensate core speed variability while matching time constraints without impacting the energy consumption. In this paper we present a new approach to compute optimal task allocations at run-time. The proposed strategy exploits an efficient and scalable implementation to find on-line the best possible solution in a tightly bounded time. Experimental results demonstrate the effectiveness of compensation both in terms of deadline miss rate and energy savings. Results have been compared with those obtained applying state-of-art techniques on a multithreaded MPEG2 decoder. The validation has been performed on a cycle-accurate virtual prototype of a next-generation industrial multicore platform that has been extended with process variability models.

Efficient data aggregation and compression in sensor networks is becoming fundamental with the increase of the number of nodes in the network. Although several data aggregation and compression techniques have been proposed in the literature only few of them can perform in-network compression and can extend lifetime without prior knowledge of the sensed data or without a central coordination. In this paper we consider a scenario where a wireless sensor network (WSN) exploits ZigBee protocols for smart building application. We study a classical gathering scheme and a distributed compressive sampling approach. We discuss limitations and we propose a new distributed mixed algorithm for in-network compression. With this algorithm each node takes a decision about which scheme to adopt aiming at the reducing the number of packets to transmit. We are interested in scalability of this new method and lifetime of the system with respect to the increase of network dimension. Simulations are performed using real data sets and results show that the use of this algorithm permits to obtain longer network lifetime with small computational complexity. The performances of the algorithm are also investigated when some sensor parameters are modified and sporadic readings rise in the network.

Summary form only given. Programmability is a key requirement for fast time-to-market and agile adaptation to rapidly evolving multimedia standards and customer expectations. Unfortunately, programmable architectures come with order-of-magnitude computational density and energy efficiency gaps with respect to custom-fit hardware. Is there a way to escape the flexibility vs. efficiency dualism? Is nano-scale silicon technology adding new facets to this “no free lunch” view? In this talk I will describe key architectural and technology cornerstones of silicon-efficient throughput computing and provide some insight on how we hope to give positive answers to these fundamental questions.

The ever-increasing complexity of MPSoCs is making the production of software the critical path in embedded system development. Several programming models and tools have been proposed in the recent past that aim at facilitating application development for embedded MPSoCs. OpenMP is a mature and easy-to-use standard for shared memory programming, which has recently been successfully adopted in embedded MPSoC programming as well. To achieve performance, however, it is necessary that the implementation of OpenMP constructs efficiently exploits the many peculiarities of MPSoC hardware. In this paper we present an extensive evaluation of the cost associated with supporting OpenMP on such a machine, investigating several implementative variants that efficiently exploit the memory hierarchy. Experimental results on different benchmarks confirm the effectiveness of the optimizations in terms of performance improvements.

Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the transmission protocol in NoCs, as it offers high throughput and low latency. To match the application characteristics, customized irregular topologies and routing functions are used. With wormhole flow control and custom irregular NoC topologies, deadlocks can occur during system operation. Ensuring a deadlock free operation of custom NoCs is a major challenge. In this paper, we address this important issue and present a method to remove deadlocks in application-specific NoCs. Our method can be applied to any NoC topology and routing function, and the potential deadlocks are removed by adding minimal number of virtual or physical channels. Experiments on a variety of realistic benchmarks show that our method results in a large reduction in the number of resources needed (88% on average) and NoC power consumption, area reduction (66% area savings on average) when compared to the state-of-the-art deadlock removal methods.

Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future scenarios. We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs.

Historically, processor performance has increased at a much faster rate than that of main memory and up-coming NoC-based many-core architectures are further tightening the memory bottleneck. 3D integration based on TSV technology may provide a solution, as it enables stacking of multiple memory layers, with orders-of-magnitude increase in memory interface bandwidth, speed and energy efficiency. To fully exploit this potential, the architectural interface to vertically stacked memory must be streamlined. In this paper we present an efficient and flexible distributed memory interface for 3D-stacked DRAM. Our interface ensures ultra-low-latency access to the memory modules on top of each processing element (vertically local memory neighborhoods). Communication to these local modules do not travel through the NoC and takes full advantage of the lower latency of vertical interconnect, thus speeding up significantly the common case. The interface still supports a convenient global address space abstraction with high-latency remote access, due to the slower horizontal interconnect. Experimental results demonstrate significant bandwidth improvement that ranges from 1.44× to 7.40× as compared to the JEDEC standard, with peaks of 4.53 GB/s for direct memory access, and 850 MB/s for remote access through the NoC.

There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumption. In this direction, this paper focuses on a GALS system where the NoC and its end-nodes have independent clocks (unrelated in frequency and phase) and are synchronized via dual-clock FIFOs at network interfaces. Within the network, we assume mesochronous synchronization implemented with hierarchical clock tree distribution. This paper contributes two essential components of any practical design automation support for network instantiation in the target system. On one hand, it introduces a switch design which greatly reduces the overhead for mesochronous synchronization and can be adapted to meet different layout constraints. On the other hand, the paper illustrates a design space exploration framework of mesochronous links that can direct the selection of synchronization options on a port-by-port basis for all the switches in the NoC, based on timing and layout constraints. A final case study illustrates how a cost-effective GALS NoC can be assembled, placed and routed by exploiting the flexibility of the architecture and the outcomes of the exploration framework, thus proving the viability and effectiveness of the design platform.

Label-free DNA detection is of crucial role to when developing point-of-care biochips to be used in personalized therapy. Capacitance detection is a promising technology for label-free DNA detection. However, data published in literature often show evident time drift, large standard deviation, scattered data points, and poor reproducibility. To solve these problems, alkanethiol molecules such as mercapto-hexanol are usually considered as blocking agents. The aim of the present paper is to investigate new blocking agents to further improve DNA probe surfaces. Data from AFM, SPR, fluorescence microscopy, and capacitance measurements are used to demonstrate the new lipoates molecules. Moreover precursor layers obtained by using Ethylene-glycol alkanethiols offer further improvements in terms of diminished detection errors. Film structure is investigated at the nano-scale to justify the detection improvements in terms of probe surface quality. This study demonstrates the superiority of lipoate and Ethylene-glycol molecules as blocking candidates when immobilizing molecular probes onto spot surfaces in label-free DNA biochip.

Several wireless sensor network (WSN) applications leverage energy harvesting technologies such as small size photo-voltaic modules. The advantage of solar energy over other forms of environmental energy is that the available solar power can be predicted with reasonable accuracy allowing the implementation of efficient power management techniques. However accurate predictions of future energy profiles can be expensive in term of memory occupancy and complexity and a trade-off between accuracy and computational effort must be evaluated. In this paper we compare different solar energy prediction algorithms that give estimates future available energy over the time. They are computationally simple and have a small memory footprint to facilitate the implementation in resource limited solar harvesting sensor nodes. Simulation results show that the most effective predictors is possible achieve high accuracy, diverging from real energy profile by less than 10%.

The ultimate goal of low-power distributed embedded systems is to develop devices which are able to operate unattended for years. Micro-energy harvesting systems can scavenge milliwatts from solar, thermal and vibrational sources and are considered as the breakthrough which will revolutionize ultra-low power systems, wireless sensor networks (WSN) and pervasive applications. This paper will demonstrate that muW harvesters are capable to power systems for operation at extremely low power levels. In particular we deal with musolar-scavengers of some mm2 which address the small energy budget optimizing the efficiency of energy collection even when tracking the maximum power point (MPP) becomes difficult and burdensome to implement. Simulations and experimental results show the impact of light intensity variations on the activity of the sensor node.

In deep submicron designs of MultiProcessor Systems-on-Chip (MPSoC) architectures, uncompensated within-die process variations and aging effects will lead to an increasing uncertainty and unbalancing of expected core lifetimes. In this paper we present an adaptive workload allocation strategy for run-time compensation of variations- and aging-induced unbalanced core lifetimes by means of core activity duty cycling. The proposed techniques regulates the percentage of idle time on short-expected-life cores to meet the platform lifetime target with minimum performance degradation. Experiments have been conducted on a multiprocessor simulator of a next-generation industrial MPSoC platform for multimedia applications made of a general purpose processor and programmable accelerators.

Design of power management mechanisms of hardware components (CPU, memories) in Embedded Systems needs to be performed at OS level to exploit system-level information. Traditional simulation models do not fit well, being too slow to simulate applications with OS-interaction. In this paper we present a high-level simulation framework that extends power state machines to hardware and software components to explore power management policies including OS-level effects faster than traditional approaches.

The goal of thermal management is to meet maximum operating temperature constraints, while at the same time tracking time-varying performance requirements. Current approaches avoid thermal violations by forcing abrupt operating points changes (e.g. processor shutdown), which cause sharp performance degradation. In this paper we aim at achieving a smooth thermal control action, that minimizes the variance of performance tracking error. We formulate this problem as a discrete-time optimal control problem, which can be solved using the theory and computational tools developed in the field of model-predictive control. Our optimization process considers the thermal profile of the system, its evolution over time, and time-varying workload requirements. Experimental results show that the proposed approach offers significant thermal balancing improvements over previous methods.

In this paper we describe a wireless wearable system to monitor gait, based on a customized pair of commercial insoles able to collect ground reaction forces by use of 24 embedded cells for each foot. Each insole was combined with a small form factor, low-power Inertial Measurement Unit (IMU) and enabled to communicate via Bluetooth with a base station. We present here the characterization of the system both in terms of performance and in terms of functionality. The system was tested on a subject to demonstrate the usability and the features extraction during gait; this data allow to recognize walking phase in terms of swing and stance phase, step and stride duration, double support and single support duration, both using the pressure sensors and the IMU.

Ultra low power digital systems are key for any future wireless sensor nodes but also inside nomadic embedded systems (such as inside the digital front end of software defined radios). These systems require the highest possible energy efficiency of logic, which can only be achieved by operating in moderate inversion. Unfortunately, when operating near the threshold voltage, transistors become highly sensitive to process variations, thereby increasing leakage currents and complicating timing closure. Rather than pursuing a worst-case design approach for dealing with these uncertainties, we present a hybrid self-timed/synchronous approach. It will be demonstrated on the VEX VLIW core designed for ultra low-power operations. Experimental results of our approach demonstrate performance benefits up to 2times and significant energy savings at low throughput rates.

Sleep transistor insertion is a key step in low power design methodologies for nanometer CMOS. In the clustered sleep transistor approach, a single sleep transistor is shared among a number of gates and it must be sized according to the maximum current that can be injected onto the virtual ground by the gates in the cluster. A conservative (upper bound) estimate of the maximum injected current is required in order to avoid excessive speed degradation and possible violations of timing constraints. In this paper the authors propose a scalable algorithm for tightening upper bound computation, with a controlled and tunable computational cost. The algorithm leverages the capabilities of state-of-the-art commercial timing analysis engines, and it is tightly integrated into standard industrial flow for leakage optimization. Benchmark results demonstrate the effectiveness and efficiency of our approach