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ISBN : 978-1-4799-3569-7, International audience, In this paper we present a new mixed design of the tone mapping technique used to adjust high dynamic range (HDR) image sensor luminosities. The dynamic range extension along with the tone mapping technique implementation allows covering correctly more than six orders of luminosity magnitude. The architecture is inspired from the human vision system operation. The proposed function and its architecture design as well as MATLAB emulation applied to images extracted from a linear CMOS image sensor designed in 0.35um AMS technology are illustrated along the paragraphs of the paper.

ISBN 978-2-9530504-1-7, National audience, The context of this paper is the dynamic assertionbased verification (ABV) of TLM SystemC models. We have developed a methodology for checking temporal properties during the SystemC simulation. The assertions are expressed in the PSL language, including the possibility to use its modeling layer, and the method supports timed as well as untimed TLM descriptions. It is implemented in a prototype tool called ISIS. We describe its principles and technical characteristics, and we report various experimental results.

ISBN : 978-0-7695-3180-9, International audience, This paper presents the challenges encountered during the process of moving an MPEG4 decoder implementation from RISC based platforms to CELL processor. It presents multiple implementations of MPEG4 video decoder on aCELL processor, using different software partitioning and mapping schemes. The approach starts from a generic representation of an MPEG4 video decoder, from which multiple customized MPEG4 video decoders can be obtained (i.e. different number of tasks, video resolutions, framerates, etc). Each of these configurations of MPEG4 videodecoders was mapped and executed on a CELL processor. During previous works, this was already realized using multi-RISC based Multi Processor System on Chip (MPSoC)platforms. However, by changing to CELL processors, new challenges and problems appeared. They must be considered and solved, in order to obtain a running MPEG4 videodecoder on CELL. This paper presents these challenges and problems, along with some solutions. Finally, some performance results are presented for different MPEG4 video decoders implementations on a CELL processor. This paper is focusing on the portation only, and does not cover the final optimization phase using CELL processor specific code optimization techniques.

ISBN: 978-0-7695-3180-9, International audience, Current embedded applications are migrating from single processor¬based systems to intensive data communication requiring multiprocessing. The performance demanded by these applications requires the use of heterogeneous multiprocessing architectures in a single chip (MPSoCs) endowed with complex communication infrastructures, such as Networks on Chip or NoCs. NoC parameter choices, such as network dimensioning, topology, routing algorithm, and buffer sizing then become essential aspects for optimizing the implementation of such complex systems. This paper presents NoC models that allow evaluating communication architectures through the variation of parameters during MPSoC design. Applicability of the concepts is demonstrated through two heterogeneous MPSoC case studies: an MJPEG decoder and an H.264 encoder.

ISBN 978-1-4244-4596-7, International audience, The goal of this work is to confront SER predictions done with MUSCA SEP3 to measures performed at high altitude (in commercial planes) by means a generic and flexible experimental testboard developed by TIMA. In this case the testboard was a memory architecture of 1 Gigabit made from SRAMs issued from two successive generations, 130 nm and 90 nm, respectively named models 1 and 2 in the following.

ISBN 978-2-9530504-1-7, National audience, This paper presents a new method for formally verifying asynchronous circuits with a symbolic model checking tool called RAT. The main idea is to use a PSL description which models the circuit and gate behaviors. For each circuit, the behavior correctness is formally checked with RAT. The gates are abstracted by their PSL properties. As the gates are assembled together to build a larger circuit, the PSL properties can also be combined to describe the resulting circuit behavior. Therefore this circuit behavior can also be checked by the same method and then abstracted by PSL properties. The method can be applied hierarchically which prevents this formal verification from any explosion of the state number. In order to illustrate this technique, a case study - a QDI controller based on communicating elements called sequencers - is presented.

ISBN : 1-4244-0387-1, Heterogeneous systems design requires executing models using different simulators. Usually, simulators are connected and synchronized together by using mechanisms such as shared memory or TCP/IP. Current approaches have many drawbacks: they are not adapted to distributed environments, the simulation performance may be very disappointing, and each simulator has its own paradigm. We propose a new approach to simulate models described with different languages such as SystemC or ESyS.NET on a distributed environment. All the models are translated into a unique internal format in order to be able to optimize a distributed and multi-paradigm simulation of the models. Optimizations include different mechanisms such as regrouping of threads in a single one while respecting the semantics of the models or the splitting of a model in order to execute it on several computer resources.

International audience

ISBN 978-0-7695-3703-0, International audience

International audience, Evaluating the robustness of digital circuits with respect to soft errors has become an important part of the design flow for many applications. The identification of the most or less critical registers is often necessary, in order to reach the lowest overheads while achieving a given application-level robustness. The goal here is to identify those soft errors actually harmful for the system, not to compute the Soft Error Rate. In this context, we investigate new approaches based on formal techniques to improve design-time robustness evaluations at least for the most critical blocks in a circuit. Preliminary results are shown, focusing on the evaluation of self-healing (or self-repairing) capabilities.

ISBN 0-7695-2566-0, International audience, We present an original transparent-based programmable memory BIST solution suitable for offline as well as online memory testing. Thanks to an appropriate combination of the test algorithm with the data backgrounds and by providing unlimited background flexibility, the proposed solution allows covering almost all existing fault models while increases the probability to also detect un-modeled faults

ISBN : 978-3-9810801-2-4, For Design-For-Test (DFT) purposes, analogue and mixed-signal testing has to cope with the difficulty of test evaluation before production. This paper aims at evaluating test measures for RF components in order to optimize production test sets and thus reduce test cost. For this, we have first developed a statistical model of the performances and possible test measures of the Circuit Under Test (a Low Noise Amplifier). The statistical multi-normal model is derived from data obtained using Monte-Carlo circuit simulation (five hundred iterations). This statistical model is then used to generate a larger circuit population (one million instances) from which test metrics can be estimated with ppm precision at the design stage, considering just process deviations. With the use of this model, a trade-off between defect level and yield loss resulting from process deviations is used to set test limits. After fixing test limits, we have carried out a fault simulation campaign to verify the suitability of the different test measurements, targeting both catastrophic and single parametric faults. Catastrophic faults are modelled by shorts and opens. A parametric fault is defined as the minimum value of a physical parameter that causes a specification to be violated. Test metrics are then evaluated for the LNA case-study. As a result, test metrics for functional measurements such as S-parameters and Noise Figure are compared with low cost test measurements such as RMS and peak-to-peak current consumption and output voltage, input/output impedance, and the correlation between current consumption and output voltage.

ISBN : 978-3-9810801-2-4, International audience, Lasers can be used by hackers to situations to inject faults in circuits and induce security flaws. On-line detection mechanisms are classically proposed to counter such attacks, and are often based on error detecting codes. However, the efficiency of such schemes has not been precisely validated against real attack conditions. This paper presents results showing that, with a given type of laser, a classical protection technique can leave open doors to an attacker. The results give also insights into the fault models to be taken into account when designing a secured circuit.

ISBN 978-1-4244-5029-9, International audience, In this paper we propose a method for evaluating test measurements for complex circuits that are difficult to simulate. The evaluation aims at estimating test metrics, such as parametric test escape and yield loss, with parts per million (ppm) accuracy. To achieve this, the method combines behavioral modeling, density estimation, and regression. The method is demonstrated for a previously proposed Built-In Self-Test (BIST) technique for $\Sigma\Delta$ Analog-to-Digital Converters (ADC) explaining in detail the derivation of a behavioral model that captures the main nonidealities in the circuit. The estimated test metrics are further analyzed in order to uncover trends in a large device sample that explain the source of erroneous test decisions.

This paper studies the defects and failure mechanisms that can occur in CMOS imager pixels. Catastrophic and parametric fault models are then considered for modelling the faulty behaviour of pixel transistors and the photodiode. Failure mechanisms specific to the photodiodes are considered. These fault models are considered for two casestudy pixels, and we study for each case catastrophic and parametric faults.

International audience, A fault tolerant routing algorithm for 2D Mesh Networks-on-Chip is presented in this work. It combines an adaptive routing algorithm with neighbor fault-awareness and a new traffic-balancing metric. To be able to cope with runtime failures that result in message corruption, the routing algorithm is enhanced with packet retransmission and a new packet recovery scheme. Simulation results, under various case studies, with different permanent, transient and intermittent link faults, and under different failure rates demonstrate the scalability and efficiency of the proposed algorithm to tolerate multiple failures likely encountered in deep submicron technologies.

ISBN du colloque : 978-1-59593-627-1, System-level design methodologies have been introduced as a solution to handle the design complexity of embedded multiprocessor SoC (MPSoC) systems. In this paper we describe a system-level design flow starting from Simulink specification, focusing on concurrent hardware and software design and verification at four different abstraction levels: Simulink Combined Algorithm and Architecture Model (CAAM), Virtual Architecture, Transaction-accurate Model and Virtual Prototype. We used two multimedia applications, Motion-JPEG and H.264, to evaluate this design flow. Experimental results show that our design flow can generate various MPSoC architectures from Simulink CAAM correctly and efficiently, allowing processor and task design space exploration at different abstraction levels.

International audience, The coming era of chips consisting of billions of gates foreshadows processors containing thousands of unreliable cores. In this context, high energy efficiency will be available, under the constraint that applications leverage the large amount of computing cores, while masking frequent faults of the chip. In this paper, an high-level method is proposed to map and manage a parallel application on an unreliable many-cores processor System on Chip. The approach takes into account versatile constraints relative to these processors (e.g. variability, core-level DVFS) and a generic algorithm is proposed. The distributed mapping process is based on the dynamic search of the best-suited processing node, upon task creation or node defect. An adaptive stop criteria is defined in order to balance the mapping impact and application efficiency gains. The validity of the proposition is assessed with high-level simulations, under different variability and application conditions.

International audience, Fault injection techniques have been proposed recently to early analyze the dependability characteristics of analog circuits. **The aim of this paper is to compare SPICE level and high level analyses for SET-like faults injections on a PLL mixed analog-digital circuit. Advantages and drawbacks will be discussed, as well as the accuracy of the high level modeling with respect to low level effects of transients due for example to energetic particle hits.

International audience, Sphinx1 is a novel pixel architecture adapted for X-ray imaging that can detect radiation by photon counting and by charge integration. In photon counting mode, each photon is compensated by one or more counter-charge packets which can be dimensioned at a level as low as 100 electrons and the number of injected counter-charge packets indicates the incoming photon energy, thus allowing a spectrometric detection. The pixel is also able to detect radiation by integrating the charges deposited by all incoming photons and converting this analog value into a digital data with a least significant bit (LSB) of 100 electrons through the use of the counter-charge concept. The pixel was simulated in both modes, and simulation results indicate an equivalent noise charge (ENC) of 48 electrons-rms, an integral nonlinearity factor (INL) < 0.15% and a static power consumption < 1 μW.

ISBN : 978-1-4799-2199-7, International audience, In this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level. Its efficiency is analyzed by injecting a single defect at the output of a multiplexer, considering all possible locations and input combinations. While at the interconnect level, fine grain redundancy is introduced which not only bypasses defects but also increases routability. Taking advantage of the sparse intra-cluster interconnect structures, routability is further improved by efficient distribution of feedback paths allowing more flexibility in the connections among logic blocks. Emulation results show a significant improvement of about 15% and 34% in the robustness of logic block and intra-cluster interconnect respectively. Furthermore, the impact of these hardening schemes on the testability of the FPGA cluster for manufacturing defects is also investigated in terms of maximum achievable fault coverage and the respective cost.

ISBN 978-1-4673-6038-8, International audience, The high cost for testing the analog blocks of a modern chip has sparked research efforts to replace the standard tests with less costly alternative tests. However, test engineers are rather reluctant to adopt alternative tests unless they are evaluated thoroughly before moving to production and they are proven to maintain test quality. This paper gives a comprehensive overview of statistical techniques based on density estimation for evaluating analog parametric test metrics during the test development phase. A large-scale simulation study is carried out for the first time with the aim to demonstrate these techniques in action.

ISBN : 978-1-4799-2078-5, International audience, Soft errors in the configuration memory of SRAM-based FPGAs cause significant and remanent application disturbances. However, classical mitigation techniques based on massive redundancy are too costly for most applications. The method presented in this paper is based on selective redundancy in partially used LUTs. It can be applied so that no hardware is added at the system level and it has been automated in standard design flows for Xilinx and Altera families. The detection of soft errors in the configuration is performed within one clock period. Experimental results on benchmark implementations are discussed, showing the good ratio between coverage and block-level overheads, with almost no impact on power and delay. The differences between applying the approach to Virtex V and Stratix IV devices are also discussed.

International audience, In this summary paper, we discuss two types of sensors that provide a built-in test solution for RF circuits. The key characteristic of the sensors is that they are non-intrusive, in the sense that they are not electrically connected to the RF circuit under test. This has the important advantage that the design of the RF circuit becomes totally independent from the design of the sensors. In other words, the RF circuit design methodology and performance trade-offs are totally transparent to the insertion of the built-in test strategy. In particular, we propose variation-aware sensors to implement an implicit functional test and a temperature sensor to implement a defect-oriented test. The proposed sensors provide DC or low-frequency measurements, thus they have the potential to reduce drastically the test cost. We discuss the principle of operation of the sensors, we provide design guidelines, and we demonstrate the concept on a set of fabricated chips. To the best of our knowledge, this is the first proof-of-concept of RF test based on non-intrusive sensors.

ISBN 978-1-4673-2084-9, International audience, Three-dimensional (3D) integration by die-/wafer-level stacking becomes a reality, as Through-Silicon-Via technologies emerge. However, poor reliability and yield of TSV interconnects remain major challenges of this promising technology. In this paper, we propose an efficient Built-In Self-Repair (TSV-BISR) strategy for TSV faults due to manufacturing and aging defects. After interconnect tests, we replace faulty TSVs with fault-free spares using shift operations. Among the benefits of this solution is that the self-repair signals are determined on-chip without any external intervention. Moreover, we show that with TSV-BISR better reparability is achieved with fewer spares than in existing TSV repair techniques. We also show that for 3D chips with interconnect reparability targets above 98% we reduce the area needed for spares and repair logic by up to 40%.

ISBN : 978-1-4799-0039-8, International audience, In this work, we will present results showing a feasibility of a MEMS microphone, based on AMS 0.35 μm CMOS standard process, with only one step of a sacrificial SiO2 maskless etching on the substrate front-side. The microphone design, modeling and simulated performance will be studied. Fabrication of test structures obtained with a SiO2 etching will be shown as well as characterizations of these test structures.

International audience, Fast Instruction Set Simulators (ISS) are a critical part of MPSoC design flows. The complexity of developing these ISS combined with the ability to extend instruction sets tend to make automated generation of ISS a need. One important part of every ISS is its instruction decoder, but as the encoding of instruction sets becomes less orthogonal because of the incremental addition of instructions, the generation of a decoder is not anymore an obvious task. In this paper, we present two automated decoder generation strategies that are able to handle non-orthogonal instruction encodings. The first one builds a decision tree that does not consider the instruction's occurrences while the second considers these frequencies. In both cases, we use binary decision diagrams to represent the instructions encodings and the complex conditions due to the non-orthogonality of the encodings in order to generate the decoders. Our experiments on the MIPS and ARM (including VFP and Neon extensions) instruction sets show that both algorithms produce efficient decoders, and that it is beneficial to consider instruction frequencies.

International audience, Embedded memories occupy the largest part of modern SoCs and include an even larger amount of transistors. As memories are designed very tightly to the technology limits, they are more prone to failures than other circuits. Thus, they concentrate the large majority of fabrication defects affecting yield adversely. Defect densities are expected to sharply increase in ultimate CMOS and post CMOS processes, resulting in high defect densities. These problems will further worsen due to stringent low-power constraints requiring drastic reduction of voltage levels. To cope with the resulting high defect densities in cost effective manner, ECC-based repair combining ECC with spare words becomes mandatory. On the other hand, coping with accelerating aging may require testing the memories during application execution, making mandatory transparent BIST Nevertheless, traditional implementations of transparent BIST do not comply with the constraints of ECC-based repair. To cope with this issue the paper proposes a transparent BIST architecture compliant with ECC-based repair.

International audience, The disruptive innovation in pacemakers and implantable cardioverter defibrillators (ICDs) will provide implants that do not require electrical leads. Main actors in the field of cardiac rhythm management (CRM) implants prepare miniaturized and autonomous leadless implants, which could be directly placed inside a human heart. Several concepts for powering stand-alone cardiac implants were proposed392 in the past, and recently the first study of an energy scavenging system placed in the human heart has been presented393. The study was conducted for a relatively large system operating at 40 Hz. We will demonstrate, that according to the heart beat acceleration spectrum obtained by placing accelerometers inside several heart cavities394, the useful vibration energy is rather localized at lower frequencies (15 to 30 Hz). We will also detail the dimensional restrictions in the case of a leadless pacemaker. Since it has to be placed into a heart through veins, the device is expected to be of cylindrical shape with a diameter of about 6 mm. We will present the design, simulation, fabrication and characterization of piezoelectric vibration energy scavenger for cardiac implants. We will discuss the energy content of the heart vibration spectrum in a view of energy harvesting. We will place emphasis on the nature of the spectrum, the energy frequencies and corresponding amplitudes. We will present an application driven design of a resonant piezoelectric energy scavenger aiming at powering a leadless pacemaker with a useable energy of few μJ per heartbeat. Such an energy scavenger consists of a piezoelectric bimorph cantilever with 20 μm thick Pb(ZrxTi1-x)O3 layers. A simulation study in both ANSYS® and Simulink® environments, has shown that the proposed design delivers the required energy.

ISBN : 978-1-4244-9485-9, International audience, The robustness with respect to SEUs (Single-Event Upset) of a self-converging algorithm is improved by fault-tolerance techniques implemented at software level. SEU-sensitivity evaluation was done by fault injection campaigns performed using a devoted test platform. Experimental results show that implementing fault-tolerance by modifying the assembly code leads to significant improvements of the fault tolerance.

International audience, High Speed Serial Links (HSSL) are found in almost all today's System-on-Chip (SoC) connecting different components: the main chip and its I/Os, chip to chip (the main chip to a companion chip, memory sharing between two chips), etc... A variety of standards exist, each of which is used for a specific application, and many parameters affect their performance. In this paper we make a comparison of three high-speed protocols, the USB 3.0, PCI Express 2.0 (PCIe) and LLI 1.0. We analyze their different parameters, mainly the data exchange protocol, errors management, the Bit Error Rate (BER), data efficiency and the quality of service (QoS) for each of the protocols. We also show the relation between these parameters and how improving one parameter could result in a degradation of another, and based on this analysis, we finish by concluding the reason why USB is used for I/Os, PCIe is used for data hungry devices and LLI for memory sharing.

ISBN 978-1-4673-4953-6, International audience, In large SoCs, managing the effects of soft-errors in flip-flops is essential, however, selective mitigation is necessary to minimize the area and power costs. The identification of the optimal set of flip-flops to protect typically requires compute-intensive fault-injection campaigns. We present new techniques which group similar flip-flops into clusters to significantly reduce the number of fault injections. The number of required fault injections can be significantly lower than the total number of flip-flops and in one industrial design with over 100,000 flip-flops, by simulating only 2,100 fault injections, the technique identified a set of 4.1% of the flip-flops, which when protected, reduced the critical failure rate by a factor of 7x.

ISBN : 978-1-4799-3569-7, International audience, In this paper we present a new mixed design of the tone mapping technique used to adjust high dynamic range (HDR) image sensor luminosities. The dynamic range extension along with the tone mapping technique implementation allows covering correctly more than six orders of luminosity magnitude. The architecture is inspired from the human vision system operation. The proposed function and its architecture design as well as MATLAB emulation applied to images extracted from a linear CMOS image sensor designed in 0.35um AMS technology are illustrated along the paragraphs of the paper.

International audience, With the upcoming FDSOI and FinFET technologies, the gap between education and industry has never been so huge. Indeed, no university is able to provide access to such technologies before the PhD programs. Moreover, the situation is similar when looking the integrated circuit design. The incredible degrees of freedom offered to designers by CAD tools and the need to ever integrate more constraints makes really challenging the design of complex integrated circuits. The universities are facing really difficult issues: designing and fabricating advanced integrated circuits with no real experience in technologies and design techniques. In this context, this paper investigates what we should teach in our nanoelectronics Master curriculum in order to efficiently prepare our students to work in this industry.

ISBN 978-1-4673-6038-8, International audience, The high cost for testing the analog blocks of a modern chip has sparked research efforts to replace the standard tests with less costly alternative tests. However, test engineers are rather reluctant to adopt alternative tests unless they are evaluated thoroughly before moving to production and they are proven to maintain test quality. This paper gives a comprehensive overview of statistical techniques based on density estimation for evaluating analog parametric test metrics during the test development phase. A large-scale simulation study is carried out for the first time with the aim to demonstrate these techniques in action.