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The authors propose test schemes for glue logic (non-boundary-scan components) interconnects. Testing these interconnects is difficult owing to reduced accessibility and glue-logic function-dependent outputs. The proposed schemes address these testability issues and provide efficient boundary-scan based techniques. The tests are applied under the B-Scan DFT (design-for-testability) environment as scan tests. Thus, issues such as ease of test vector generation, test vector loading time, and test application time are very important for the proposed schemes. The application of the test schemes is described. >

A cell-based test design method which is consistent with features of cell-based design is introduced. By improving shift register latches, a scan test for asynchronous circuits, as well as delay tests can be executed effectively. Also, by employing a test bus and a selector shift register configuration, a multiple scan-path test is realized attractively, which drastically reduces the execution time of the scan test. This results in the possibility of realizing a hierarchical test design in which the test vectors of module circuits are saved as library data and used in the preparation of the test vector of a newly developed chip and of the schematic and artwork data. It appears that the area overhead and the increase in test time are reasonable for future VLSI chips with the complexity of 1M transistors. >

A novel framework for analyzing test generation and diagnosis algorithms for wiring interconnect are presented. A property of test vector sets, called diagonal independence, which guarantees the diagnostic resolution of the vector test set is identified. The failing responses or syndromes are classified into aliasing and confounding syndromes, and this classification permits precise analysis of the diagnostic capabilities of different test algorithms. Using this framework, all the algorithms that have been proposed for board interconnect testing are analyzed. Their capabilities and limitations are clearly defined. A new optimal adaptive algorithm that can reduce test and diagnosis complexity is also presented. >

It is noted that, to test wiring interconnects in a printed circuit board, especially one equipped with boundary-scan devices, it is important to minimize the test size while maintaining diagnostic capability. This has provided the motivation for research work that explores efficient test generation and diagnosis algorithms. The authors propose a unified theory for designing various types of interconnect test algorithms. They demonstrate that the algorithms proposed in the literature are special cases of the general algorithms given in the present work. The new algorithms are shown to be optimal or near optimal for a given set of design and process parameters. They increase the designer's flexibility by offering a full range of solutions (i.e., test vector sets) based on various tradeoff criteria, such as test compactness and diagnostic accuracy. Parameters for quantifying the quality of the tests are described. The significance and limitations of the proposed algorithms are also discussed. >

A description is given of the LAST system, a linear string of systolic processors connected together to provide a stimulus/response testing function to a device under test (DUT). LAST addresses a major problem in tester design by reducing the data transfer/storage requirements. LAST accomplishes this by converting the rhythm and regularity found in VLSI and ASIC (application-specific integrated circuit) test vector patterns into independent systolic processor rhythms. This rhythm conversion reduces the data processing and handling by orders of magnitude. LAST integrates an APG (automatic pattern generator) function at each channel, which reduces vector memory requirements for the regular test vector structures encountered in today's ASIC parts. >

A testable structure is presented for programmable logic arrays (PLAs) which is amenable to production testing. A low overhead structure is proposed to keep the kill area at the lowest value. This is achieved by using a single additional input line to the original PLA. Fault detection is based on a specific set of conditions which must be satisfied in the characteristic matrix and structure of the minimized PLA. The characteristics of the vectors in the test set are discussed. A two-phase test is used to supplement the basic test vector if the specified constraint in the minimized PLA structure is not met. Hardware overhead is lower than any other method found in the technical literature. >

CMOS failure modes and mechanisms and the test vector and parametric test requirements for the detection are reviewed. The CMOS stuck-open fault is discussed from a physical viewpoint, with results given from failure analysis of ICs having this failure mode. The results show that among functional, stuck-at, stuck-open, and I/sub DDQ/ test strategies, no single method guarantees detection of all types of CMOS defects. The I/sub DDQ/ test is the most sensitive and comprehensive, but can miss certain open-circuit defects and is a relatively slow measurement technique. The test-vector approach detects fewer of the CMOS defects, but can run at fast clock rates to detect certain open-circuit faults that may not be detectable by the I/sub DDQ/ test. Maximal CMOS IC defect detection involves a mixed-mode strategy of I/sub DDQ/ tests and vector stimulus/response tests. >

A built-in self-test of interconnects based on boundary scan architecture is described. Detection and diagnosis schemes are proposed which provide minimal-size test vector sets. I/O scan chains order independent test vector sets and walking sequences. Properties like ease of test vector generation, structure-independent detection and diagnosis, and local response compaction have made the developed schemes suitable for built-in-self-test implementation. An example board-interconnect test session is described using one of the proposed schemes. >

A simulation-based directed search approach for generating test vectors for combinational circuits has been proposed. In this method, the search for a test vector is guided by a cost function computed by the simulator. Event-driven simulation deals with circuit delays in a very natural manner. Signal controllability information required for the cost function was incorporated in a form of logic model called the threshold-value model. These concepts are now extended to meet the needs of sequential circuit test generation. Such extensions include handling of unknown values, analysis of feedback loops, and analysis of race conditions in the threshold-value model. A threshold-value sequential test generation program, TVSET, is implemented. It automatically initializes the circuit and generates race-free tests for synchronous and asynchronous circuits. >

Different sets of testability conditions for two-dimensional bilateral arrays are presented. Conditions are established with respect to the dependency of the testing process on the signal flow. Each set of testability conditions establishes the controllability and observability of a test vector. These conditions are proved to be applicable under different processing models related to the three inputs of each cell in the array. Complexity issues, such as number of test vectors and time units, are discussed. >

Novel voltage contrast image-based methods have been developed concerning voltage contrast image acquisition using electron beam tester and concerning fault searching on a VLSI chip, and have been applied to real faults of passivated VLSI devices. The developed voltage contrast image acquisition methods have shorten the acquisition time about 1200 times faster than that of the conventional stroboscopic methods and have given better image quality that that of conventional method. The method employed continuous e-beam scanning and gated sampling image signal technique (CGFI) technique. The continuous e-beam scanning may prevent the fading voltage contrast and give good voltage contrast image. The method also employed test vector shortening technique, which has a merit in shortening testing time and avoiding wrong fault tracing back. >

The importance of test in ASIC and IC design is discussed, and some new design-for-test (DFT) strategies are presented. The advantages of a specific method for test vector creation and validation that tightly links two scan-test tools into the target design flow are described. These tools are a sequential, partial-scan automatic test pattern generator (ATPG) and an ATPG optimized for full-scan designs. Some customer results with these tools are presented as well. >

Discusses a test pattern generation (TPG) algorithm for single stuck-at faults in combinational logic circuits. Current TPG systems generate a test vector for fault F/sub i+1/ independently of the computation previously done for faults F/sub 1/, F/sub 2/, . . ., F/sub i/. The algorithm ITPG, generates a test vector for fault F/sub i+1/ by starting with (inheriting) the test vector for fault F/sub i/. A new test vector is generated from inherited values by gradually changing the inherited values. The inherited values may partially activate a fault and propagate the fault signal. Normally, this reduces the number of decision steps and backtracks in the second search. Experimental results for well-known benchmark circuits show that ITPG is very efficient with a small backtrack limit; in combination with other algorithms, it is very efficient for arbitrary backtrack limits. >

A new Built-In Self Test (BIST) technique suitable for high performance DSP datapaths is presented. The BIST session is controlled via hardware without the need for a separate test pattern generation register or test program storage. Furthermore, the BIST scenario is appropriately set-up so as to also test the register file as well as the shift and truncation logic in the datapath. The use of DP-BIST enables a very high speed test (one test vector is applied per clock cycle) with no performance degradation and little area overhead for the hardware test control. Comparison between DP-BIST and scan based BIST technique is also presented. We show how DB-BIST can be used a centralized test resource to test other macros on the chip and the integration of DP-BIST with internal scan and boundary scan is addressed.

The layout of a circuit can influence the probability of occurrence of faults. In this paper, we develop algorithms that can take advantage of this fact to reduce the chances of hard-to-detect (HTD) faults from occurring. We primarily focus on line bridge faults in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern generator fails to generate a test vector for f in a reasonable amount of CPU-time. It is common practice to drop such HTD faults from consideration during test generation. The chip fault coverage achieved by a test set is poor if the fault set consists of many HTD faults. We can combat this problem by avoiding altogether, or by reducing the probability of, the occurrence of HTD faults. In this paper, we consider hard-to-detect bridging faults and show how module placement rules can be derived to reduce the probability of these faults. A genetic placement algorithm that optimizes area while respecting these rules is presented. The placement algorithm has been implemented for standard-cell layout style on a SUN/SPARC and tested against several sample circuits.

Published research on delay fault testing has largely focused on generating a minimal set of test vector pairs to detect as many delay faults in a circuit as possible. Little regard has been paid to the diagnosability of delay faults in the quest for generating tests which can simultaneously detect a delay fault on many paths, one loses the ability to determine which paths caused a chip failure. In an earlier work [1996] we presented a framework to detect which paths are likely to have caused a chip failure for a set of delay fault tests, and to find the associated likely fabrication process parameter variations. Here, we quantify the diagnosability of a path delay fault for a test, and develop a methodology based on the diagnosis framework presented earlier to determine the diagnosability of each path delay fault detected by a given test set. Furthermore, we apply this approach to find the diagnosability of robust path delay faults for the ISCAS'89 benchmark circuits.

Published research on delay fault testing has largely focused on generating test vector pairs (called delay fault tests) to detect delay faults in a circuit. Little attention has been paid to the diagnosability of delay faults-in the quest for generating tests which can simultaneously detect a delay fault on many paths, one loses the ability to determine which paths caused a chip failure. Since fabrication process perturbations contribute to the occurrence of delay faults, one would also like to determine the likely fabrication process parameter values given that a chip has failed for a set of delay fault tests. We present a framework to detect which parts of the circuit are likely to have caused a chip failure for a set of delay fault tests, and to find the associated fabrication process parameter deviations from their nominal values. This diagnosis is done by using a path sensitization mechanism to find the path delay conditions for which the chip exhibits a delay fault for a subset of the applied tests, followed by a statistical analysis to locate the likely fabrication process parameter value combinations and the parts of the circuit which are likely to have caused the failure. We present results of experiments performed an some ISCAS'89 benchmark circuits, and also relate the slack of a path segment to its probability of contributing to the circuit failure.

We propose a new statistical technique for estimating fault coverage in combinational circuits. Our method requires fault-free simulation of a random sample of vectors from the test vector set. Fault coverage is computed from controlabilities and observabilities both defined as probabilities and the method is applicable to any fault model like stuck-at-faults or delay faults. Experimental results are presented for path and transition delay faults. >

Increasing controllability in the time dimension (CTD) helps test generation either by temporarily reducing the search space through freezing state variables or by simplifying the time-frame-expansion. CTD can be increased via controlling clock lines through a well defined DFT scheme, called clock line control (CLC). The design issues for controlling clock lines have been addressed. CLC can be extended to test delay faults without causing the test vector application problems as in scan design. Experimental results using ISCAS-89 circuits are shown. Better fault coverage with shorter ATG time have been achieved for the circuits with enhanced CTD

We describe a continuous optimization approach for the test generation of combinational circuits. We extend the domain of signal values from the traditional Boolean 0 or 1 value to the real unit interval /spl lsqb/0, 1/spl rsqb/. Responses of Boolean gates comprising the circuit are also extended to deal with real input values. Non-linear smooth functions are constructed for every gate. A non-linear continuous function for the entire circuit is obtained as a summation of the individual gate functions. A similar function is derived for the faulty circuit. We construct an objective function using the good and faulty circuit functions. The objective function is minimized when at least one of the corresponding outputs of the good and faulty circuit differ. The test generation problem is formulated as the minimization of the objective function over a unit hypercube in the Euclidean space. The dimension of the space is equal to the number of primary inputs of the circuit. We optimize the smooth function inside a convex polytope using a variant of gradient descent and line search strategies. We start at the center of the hypercube and follow a trajectory to one of the corners of the hypercube that corresponds to a test vector. Preliminary experimental results on the ISCAS '85 and '89 benchmark circuits demonstrate the feasibility of our approach. >

Partial scan design technique is often preferred to full scan because the use of smaller number of scan flip-flops leads to less performance degradation and less overhead. However, the number of clocks required to apply a test vector is proportional to the number of flip-flops in the scan path whenever scan is performed. This tends to increase the test application considerably. In this paper we presents an algorithm to generate a test with fewer test clocks for partial scan designs by using sequential test generation and scan strategies. The objective is to find a test that requires less test clocks while achieving high fault coverage. The algorithm, Test Application time Reduction for Partial scan design (TARP), is implemented and tested on a set of ISCAS sequential benchmark circuits. The algorithm produces a test with substantial reduction in the number of test clocks, compared to a test in which each test vector is associated with a scan operation. >

This paper presents a partial scan algorithm, called PARES (Partial scan Algorithm based on REduced Scan shift), which designs partial scan circuits and generates short test sequences. PARES is based on the reduced scan shift, in which flip flops (FFs) required to be controlled and observed are determined for each test vector in order to reduce scan shift operations. PARES selects FFs which are more frequently required to be controlled or observed as a scanned FF. Short test sequence can be obtained by reducing scan shift operations. Since fault coverage may be not possibly high because of unscanned FFs, techniques to increase fault coverage are also proposed. The order of test vectors are determined such that the values of unscanned FFs after applying a test vector is equivalent to next applied test vector. Moreover, appropriate values are assigned to primary inputs in scan shift operations in order to detect more faults. Finally experimental results for ISCAS'89 benchmark circuits are given. >

This paper presents a method of test compaction for stuck-at faults in combinational circuits, that complements previously proposed methods and allows further reduction in test set size in a cost-effective way. A given test set is compacted by generating additional test vectors. Each test vector added allows the removal of two or more test vectors from the existing test set, thus reducing its size. Experimental results for benchmark circuits demonstrate the effectiveness of the method. >

Methods are investigated for reducing events in sequential circuit fault simulation by reducing the number of faults simulated for each test vector. Inactive faults, which are guaranteed to have no effect on the output or the next state, are identified using local information from the fault-free circuit in one technique. In a second technique, the Star-algorithm is extended to handle sequential circuits and provides global information about inactive faults, based on the fault-free circuit state. Both techniques are integrated into the PROOFS synchronous sequential circuit fault simulator. An average 28% reduction in faulty circuit gate evaluations is obtained for the 19 ISCAS-89 benchmark circuits studied using the first technique, and 33% reduction for the two techniques combined. Execution times decrease by an average of 17% when the first technique is used. For the largest circuits, further improvements in execution time are made when the Star-algorithm is included. >

Minimal test sets have the property that each input test vector tests simultaneously several faults in a circuit. Existing techniques use Boolean simplification or Karnaugh maps to achieve minimization. The authors present two new methods, one of which is a simple design by inspection technique and the other is a graphical technique. The process of minimization has been simplified by adopting the unique approach of first finding all the faults that can be detected by a single test. >

The authors propose a novel linear-time algorithm for identifying, in a large combinatorial circuit, a large set of faults that are undetectable by a given test vector. Although this so-called X-algorithm does not identify all the undetectable faults, empirical evidence is offered to show that the reduction in the number of remaining faults to be simulated is significant. The algorithm is intended as a simple, fast preprocessing step to be performed after a test vector has been generated, but before the (often lengthy) process of fault simulation begins. The empirical results indicate that the X-algorithm is both useful (indicated by the utility factor) and good (indicated by the effectiveness factor). It provides as much as a 50% reduction in the number of faults that need to be simulated. Moreover, the algorithm seems to identify a large fraction of the undetectable faults. >

The authors describe a high-level test vector description language, Wave+, that is specially tailored to the development of vector generators for ASIC (application-specific integrated-circuit) cell compilers. The motivation for such a language is described, along with special problems inherent in compiled cells, which may have variable function and port configuration. Various features of the language, including its abstract transition-oriented and block-oriented vector model and its control structures, are described. The advantages of the language including its simplicity and intuitiveness, which make it easy to use, for compiler design engineers with little software expertise are summarized. >

A novel approach is presented to minimize the 100% single-stuck (SS) fault test vector set of a synthesized circuit during the logic synthesis process. In the synthesis process for any given two-level primary and irredundant (PI) network, the authors first define a specific SS fault test vector set of the two-level network and prove that it is a superset of the 100% SS fault test vector set for the synthesized circuit. Instead of generating all the vectors in this superset, they develop an algorithm to minimize this superset during the logic optimization and technology mapping process. Then, they generate the test vectors by using a two-level test generator. The experimental data demonstrates that the resultant number of test vectors can be up to 40% less than that of the conventional method such as PODEM in many cases, while the additional CPU time used for test vector generation is about 5% of the conventional method on average. >

The authors describe the Waveform and Vector Exchange Specification (WAVES), a proposed standard for the exchange of simulation and test vector information. They address the history of the WAVES effort, its requirements and objectives, the general architecture of WAVES data sets, and the WAVES design rationale. WAVES data sets describe waveforms (event streams) by defining the time histories of collections of logic signals. The waveform description style provided by WAVES supports an information model which captures all the information in the simulator stimulus languages and tester test vector languages, including multilevel value systems, tester formats, repeat and branch capabilities, and hierarchical test organization. An example shows how WAVES supports translation from ATE (automatic test equipment) test vectors to WAVES. >

This paper presents three built-in self-test (BIST) schemes for robust testing of stuck-open faults in combinational FCMOS complex cells of arbitrary structure. The first method shows that all single stuck-open faults can be robustly tested by applying a universal sequence of 5/spl times/2/sup n/ vectors to the modified circuit under test (CUT), and counting the number of 1's in the output response. The second method uses the same test pattern generator (TPG), but faults are detected by a self comparison technique without the need of storing a signature. Finally, we propose a new adaptive BIST technique, where the TPG is driven by the past outputs of the CUT itself In all the cases, the TPG is universal, i.e., if does not depend on the functionality and the structure of the CUT, but does ensure robust testing. Neither any test vector, nor any fault dictionary, is required. These approaches provide simplicity, less testing time and test data, and compare favorably with earlier BIST designs for CMOS circuits.

Existing one-step diagnosis approaches for faults in interconnects either yield a long test sequence, or use a non-generalized procedure to generate a shorter test sequence. We propose a new diagnosis approach for short faults in interconnects. The pin-adjacency fault model is assumed. By using a divide-and-conquer strategy, our approach can generate a very compact test vector sequence which can diagnose an unrestricted number of short faults. Our experiments for three benchmarks as well as large random interconnects (up to 50,000 nets) show that our approach can achieve more than 50% savings in the length of the generated test sequence. This can significantly save the diagnosis cost for boundary-scan testing. An adaptive diagnosis approach is further proposed to dynamically truncate the originally generated test sequence based on the current information of faulty nets. The performance of our adaptive approach in terms of the on-line test generation time and the resulting test sequence length is better than for existing adaptive diagnosis approaches when the fault rate is not very small, such as in a new product line. If a low complexity for the ATE is of major importance, then the proposed one-step approach is the best choice. >

Full scan and partial scan are effective design-for-testability techniques for achieving high fault coverage. However, test application time can be high if long scan chains are used. Reductions in test application time can be made if flip-flop values are not scanned in and out before and after every test vector is applied. Previous research has used deterministic fault-oriented combinational and sequential circuit test generators in generating test vectors and sequences and in deciding when to scan the flip-flops. In this work we use genetic algorithms to generate compact test sets which limit the scan operations. Results for the ISCAS89 sequential benchmark circuits show that significant reductions in test application time can be achieved, especially for partial scan circuits.

In this paper we propose a new apparatus for embedding deterministic patterns in pseudo-random sequences, with application to at-speed BIST. We employ an arbitrary length Shift Register driven by a LFSR (LFSR/SR) with the size of the LFSR dependent only on the number of care bits in any test vector. We provide an efficient method to compute positions of bit-patterns at arbitrarily chosen tap configurations in the LFSR/SR sequence. Hence, one can make an optimal choice of test segments (seeds) while taking inherent advantage of don't care bits in test vectors, say corresponding to random pattern resistant faults. The length of the LFSR/SR can be arbitrarily increased to feed several interconnected logic blocks such that all the care bits of any deterministic test vector can be predictably generated without compromising computational efficiency.

This paper addresses the issue of reducing test application time in sequential circuits with partial scan using a single clock configuration without freezing the state of the non-scan flip-flops. Experimental results show that this technique significantly reduces test application time. Further, we study the effect of ordering the scan flip-flops on the test vector length and also present a non-atomic two-clock scan method which can be easily incorporated in conventional test generation environment.

This paper proposes a generalization of robust tests with respect to assumptions about fault models and circuit models. The specific case of d-robust tests for single stuck-at faults is studied. These tests maintain their validity in the presence of macro-delay faults. A macro-delay of size n means that the delay of all combinational paths can be in the range [O,nT] where T is the clock period. We give a simple method of duplicating a test vector n times to produce a d-robust test for a stuck-at fault in a combinational circuit. We further implement a more complex algorithm to derive d-robust tests for stuck-at faults in sequential circuits.

The majority of design for testability (DFT) methods for sequential circuits are based on scan designs (complete or partial). Nevertheless, with these methods the test application time remains often prohibitive due to the long shift operation to enter the test vector into the scan register. In this paper, we present a DFT method which modifies the circuit in such a way that, during the test operation, several more easily testable configurations are emulated. Different implementations are proposed for these test configurations that are shown to be useful to improve either the controllability or the observability. The efficiency of the method is evaluated in terms of fault coverage, number of modified flip-flops and test application time, using ISCAS89 benchmarks.

We propose a procedure to generate compact test sets for bridging faults under I/sub DDQ/ testing. Several techniques are employed to achieve compact test sets. Heuristics developed for stuck-at faults are shown to be effective in this context. The techniques especially designed for bridging faults are based on the observation that the yet-undetected faults can be represented using sets of lines and that a minimum test set size is obtained if the line sets representing yet-undetected faults are halved with every additional test vector. Logic blocks called bit-adders allow the partitioning of the line sets using a test generator for stuck-at faults, without having to determine in advance how the lines in a given set will be divided. Thus partitioning can be performed in a cost effective way for any line set size. Experimental results show that the test sets generated by the proposed procedure are smaller than those obtained by previously proposed procedures.

The generation of test patterns for digital circuits is known as an NP hard problem. Due to the backtracking mechanism in the sequential algorithms for test pattern generation it is difficult to speed up the process. In this paper we present a parallel formulation of the FAN algorithm implemented on a heterogeneous cluster of workstations. Two different methods are used to take into account easy- and hard-to-detect faults. We show the strategies for our parallel implementations as well as implementation details. Linear speedups are shown with the results. Furthermore we introduce a new method for test vector compaction using a genetic algorithm. This results in smaller test sets compared to traditional methods. The reader should be familiar with notations of the FAN algorithm.

This paper discusses a novel testing technique for analogue circuits. The theory behind its success in exposing defects normally unexposed by other testing techniques is presented. This is supported by simulation results and real IC tests. Due to its modest requirement to perform the test, this testing scheme is more attractive and beneficial. Methods of data analysis are also proposed to expose hard and soft defects. The advantages of the proposed testing scheme are fast to implement, uses simple test vector and does not require additional test circuitry on-chip.