1. A 800 MHz system-on-chip for wireless infrastructure applications
- Author
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M. Krishnan, Joel J. Graber, Maria B. H. Gill, Jose Luis Flores, Usha Narasimha, S. Mullinnix, Sanjive Agarwala, Arjun Rajagopal, Raguram Damodaran, J. Apostol, Anthony M. Hill, P. Wiley, B. Webster, Heping Yue, Luong Tan Nguyen, Lewis Nardini, T. Kroeger, N.S. Nagaraj, Abhijeet Ashok Chachad, K. Castille, C. Karlovich, Timothy D. Anderson, P. Groves, and T. Wolf
- Subjects
CMOS ,Very long instruction word ,business.industry ,Computer science ,Embedded system ,Hardware_INTEGRATEDCIRCUITS ,Bandwidth (computing) ,8-bit ,Wireless ,System on a chip ,Chip ,business ,Digital signal processing - Abstract
The 800MHz System-on-Chip implements the C64x VLIW DSP VelociTI.2/spl trade/ Architecture and delivers 6400 MIPS, 3200 16-bit MMACs, 6400 8-bit MMACs at 0.17 mW/MMAC (8 bit). The chip is implemented in state of the art 90 nm CMOS technology with 7-layer copper metalization. The core dissipates 1080 mW at 800 MHz, 1.2V. The system-on-chip is targeted for high performance wireless infrastructure application. It has an 8-way VLIW DSP core, a 2-level memory system, and an I/O bandwidth of 3.2GB/s.
- Published
- 2004
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