417 results on '"turnaround time"'
Search Results
2. Levelized Multiple Workflow Allocation Strategy Under Precedence Constraints With Task Merging in IaaS Cloud Environment
- Author
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Faisal Ahmad, Mohammad Shahid, Mahfooz Alam, Zubair Ashraf, Mohammad Sajid, Ketan Kotecha, and Gaurav Dhiman
- Subjects
Cloud computing ,IaaS cloud environment ,multiple workflow allocation ,task merging ,levelized DAG scheduling ,turnaround time ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
Cloud Service Providers are speedily becoming the target platform for scientific workflow computations due to the massive possible and flexible pay-as-you-go pricing model. Workflow allocation problem in cloud systems is considered NP-hard. A heterogeneous IaaS cloud could be fully effective if the allocation method provides an efficient mapping between virtual machines (VMs) and workflow applications demanding execution. First, we model multiple workflow allocation problem in the cloud environment. Then, we propose a levelized multiple workflow allocation strategy with task merging (LMWS-TM) to optimize turnaround time for multiple workflow applications in the Infrastructure as a Service (IaaS) cloud environment to achieve better performance. The task merging scheme is incorporated into workflows after partitioning and prior to allocation to reduce inter-task communication share and the total number of depth levels for improving the overall completion time. Moreover, it considers inter-task communication and inter-machine distance for estimating communication cost share among tasks on the schedule generated. Furthermore, the scheme is capable enough to use simple and flexible level attributes to tackle precedence constraints. Afterward, we conducted an experimental study to evaluate LMWS-TM by comparative performance analysis with its peers, namely SLBBS, DLS, and HEFT, on quality of service (QoS) parameters, namely, turnaround time, system utilization, flow time, and response time. The study reveals the superior performance of LMWS-TM among its considered peers in almost all the cases for almost all considered parameters under investigation. Finally, we performed statistical testing to test the significance level using SPSS 20, confirming the hypothesis drawn in the experimental study.
- Published
- 2022
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3. Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network.
- Author
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Jiang, Bentian, Liu, Lixin, Ma, Yuzhe, Yu, Bei, and Young, Evangeline F. Y.
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PHYSIOLOGICAL effects of acceleration , *TURNAROUND time , *DEEP learning - Abstract
Optical proximity correction (OPC) in modern design closures has become extremely expensive and challenging. Conventional model-based OPC encounters performance degradation and large process variation, while aggressive approach, such as inverse lithography technology (ILT), suffers from large computational overhead for both mask optimization and mask writing processes. In this article, we developed Neural-ILT, an end-to-end learning-based OPC framework, which literally conducts mask prediction and ILT correction for a given layout in a single neural network, with the objectives of: 1) mask printability enhancement; 2) mask complexity optimization; and 3) flow acceleration. A domain-specific model pretraining recipe, which introduces the domain knowledge of lithography system, is proposed to help Neural-ILT achieving faster and better convergence. Quantitative results show that compared to the state-of-the-art (SOTA) learning-based OPC solutions and conventional OPC flows, Neural-ILT can achieve $15\times $ to $30\times $ turnaround time (TAT) speedup and the best mask printability with relatively lower mask complexity. Based on the developed infrastructure, we further investigated the feasibility of handling multiple mask optimization tasks for different datasets within a common Neural-ILT platform. We believe this work could bridge well-developed deep learning toolkits to GPU-based high-performance lithographic computations to achieve groundbreaking performance boosting on various computational lithography-related tasks. [ABSTRACT FROM AUTHOR]
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- 2022
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4. Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis.
- Author
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Cheng, Chung-Kuan, Ho, Chia-Tung, Holtz, Chester, Lee, Daeyeal, and Lin, Bill
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MOORE'S law ,SENSITIVITY analysis ,MACHINE learning ,BOOSTING algorithms ,TURNAROUND time - Abstract
As technology nodes continue to advance relentlessly, geometric pitch scaling starts to slow down. In order to retain the trend of Moore’s law, design technology co-optimization (DTCO) and system technology co-optimization (STCO) are introduced together to continue scaling beyond 5 nm using pitch scaling, patterning, and novel 3-D cell structures [i.e., complementary-FET (CFET)]. However, numerous DTCO and STCO iterations are needed to continue block-level area scaling with considerations of physical layout factors: 1) various standard cell (SDC) library sets (i.e., different cell heights and conventional FET); 2) design rules (DRs); 3) back end of line (BEOL) settings; and 4) power delivery network (PDN) configurations. The growing turnaround time (TAT) among SDC design, DR optimization, and block-level area evaluation becomes one of the major bottlenecks in DTCO and STCO explorations. In this work, we develop a machine learning model that combines bootstrap aggregation and gradient boosting techniques to predict the sensitivity of minimum valid block-level area of various physical layout factors. We first demonstrate that the proposed model achieves 16.3% less mean absolute error (MAE) than the previous work for testing sets. Then, we show that the proposed model successfully captures the block-level area sensitivity of new SDC library sets, new BEOL settings, and new PDN settings with 0.013, 0.004, and 0.027 MAE, respectively. Finally, compared to the previous work, the proposed approach improves the robustness of predicting new circuit designs by up to 6.76%. The proposed framework provides more than $100\times $ speedup compared to conventional DTCO and STCO exploration flows. [ABSTRACT FROM AUTHOR]
- Published
- 2022
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5. Parallel Velocity Extension for Level-Set-Based Material Flow on Hierarchical Meshes in Process TCAD.
- Author
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Quell, Michael, Suvorov, Vasily, Hossinger, Andreas, and Weinbub, Josef
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SILICON nanowires , *FLOW simulations , *VELOCITY , *INTEGRATED circuits , *TURNAROUND time , *COMPUTER-aided design - Abstract
The level-set method is widely used for high-accuracy 3-D topography simulations in process technology computer-aided design (TCAD) because of its robustness to topological changes introduced by the involved complicated physical phenomena. Particularly challenging are material flow processes, such as oxidation, reflow, and silicidation, as these require the solution of intricate physical models and the extension of the model-dependent velocity fields to the entire simulation domain at every time step to accurately compute the advection. This velocity extension, thus, introduces yet another computational burden at every time step, which is significant when considering that high-accuracy material flow simulations can easily require several hundred time steps and are applied multiple times in cutting-edge fabrication processes of integrated circuits. In this work, a shared-memory parallel scalar and vector velocity extension algorithm for level-set-based material flow simulations on hierarchical meshes is introduced, allowing to further reduce the turnaround time of TCAD workflows. The performance is evaluated by investigating a representative material flow simulation of 3-D thermal oxidation of silicon. A parallel speedup of 7.1 for the vector-valued extension and 6.6 for the scalar-valued extension is achieved for ten threads; the latter outperforms a previous approach by up to 60%. [ABSTRACT FROM AUTHOR]
- Published
- 2021
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6. Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules.
- Author
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Park, Dongwon, Lee, Daeyeal, Kang, Ilgweon, Holtz, Chester, Gao, Sicun, Lin, Bill, and Cheng, Chung-Kuan
- Subjects
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INTEGRATED circuit design , *BOTTLENECKS (Manufacturing) , *LINEAR programming , *TURNAROUND time , *INTEGER programming , *FLUX pinning , *SCALABILITY - Abstract
Pin accessibility encounters nontrivial challenges due to the smaller number of routing tracks, higher pin density, and more complex design rules. Consequently, securing design rule-correct routability has become a critical bottleneck for sub-10-nm IC designs (particularly in the detailed routing stage) costing days of runtime. To reduce turnaround time, IC designers demand new design methodologies to analyze the routing feasibility of a given layout architecture (e.g., conditional design rules, pin assignment patterns, etc). There are several conventional methods capable of assessing routability that consider pin accessibility. However, precise diagnosis of unroutable layouts remains an open problem for IC design practitioners. In this article, we propose two novel frameworks that: 1) efficiently analyzes design rule-correct routability via an integer linear programming (ILP)-derived Boolean satisfiability (SAT) formulation written in light-weight conjunctive normal form, on top of multicommodity flow theory and 2) precisely diagnose explicit reasons for design-rule violations (DRVs) in the form of human-interpretable explanations, while specifying conflicting design rules with a physical location. While covering a variety of conditional design rules, we have refined our formulation by using SAT encoding techniques, supernode simplification, Boolean constraint propagation-based preprocessing, etc. We demonstrate that our routability analysis framework produces design rule-correct routability assessment within 0.02% of ILP runtime on average. Also, our routability diagnosis framework precisely examines DRVs, revealing design-rule conflicts for a variety of pin layouts and switchboxes. We show our frameworks scalability by utilizing practical benchmarks ranging up to 40 000 grid-size layouts (i.e., 200 Htrack $\times $ 200 Vtrack), producing results within an hour. [ABSTRACT FROM AUTHOR]
- Published
- 2020
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7. An Approach to Achieve Zero Turnaround Time in TDD Operation on SDR Front-End
- Author
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Muhammad Aslam, Xianjun Jiao, Wei Liu, and Ingrid Moerman
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RF front-end ,SDR ,TDD ,turnaround time ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
Thanks to the digitization and softwarization of radio communication, the development cycle of new radio technologies can be significantly accelerated by prototyping on software-defined radio (SDR) platforms. However, a slow turnaround time (TT) of the front-end of an SDR for switching from receiving mode to transmitting mode or vice versa, are jeopardizing the prototyping of wireless protocols, standards, or systems with stringent latency requirements. In this paper, a novel solution called BaseBand processing unit operating in Half Duplex mode and analog Radio Frequency front-end operating in Full Duplex mode, BBHD-RFFD, is presented to reduce the TT on SDR. A prototype is realized on the widely adopted AD9361 radio frequency frontend to prove the validity of the proposed solution. Experiments unveil that for any type of application, the TT in time division duplex (TDD) operation mode can be reduced to zero by the BBHD-RFFD approach, with negligible impact on the communication system in terms of receiver sensitivity. The impact is measured for an in-house IEEE 802.15.4 compliant transceiver. When compared against the conventional TDD approach, only a 7.5-dB degradation is observed with the BBHD-RFFD approach. The measured sensitivity of -91 dBm is still well above the minimum level (i.e., -85 dBm at 2.4 GHz) defined by the IEEE 802.15.4 standard.
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- 2018
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8. Design Space Exploration for Chiplet-Assembly-Based Processors.
- Author
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Pal, Saptadeep, Petrisko, Daniel, Kumar, Rakesh, and Gupta, Puneet
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SYSTEMS on a chip ,TURNAROUND time ,MULTIPURPOSE buildings ,SYSTEMS design - Abstract
Recent advancements in 2.5-D integration technologies have made chiplet assembly a viable system design approach. Chiplet assembly is emerging as a new paradigm for heterogeneous design at lower cost, design effort, and turnaround time and enables low-cost customization of hardware. However, the success of this approach depends on identifying a minimum chiplet set which delivers these benefits. We develop the first microarchitectural design space exploration framework for chiplet assembly-based processors which enables us to identify the minimum set of chiplets to design and manufacture. Since chiplet assembly makes heterogeneous technology and cost-effective application-dependent customization possible, we show the benefits of using multiple systems built from multiple chiplets to service diverse workloads (up to 35% improvement in energy-delay product over a single best system) and advantages of chiplet assembly approaches over system-on-chip (SoC) methodology in terms of total cost (up to 72% improvement in cost) while satisfying the energy and performance constraints of individual applications. [ABSTRACT FROM AUTHOR]
- Published
- 2020
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9. Assessment of an Improved Finite Control Set Model Predictive Current Controller for Automotive Propulsion Applications.
- Author
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Andersson, Andreas and Thiringer, Torbjorn
- Subjects
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PREDICTION models , *PULSE width modulation transformers , *TURNAROUND time , *DOUBLE standard , *PULSE width modulation - Abstract
This paper presents an investigation on finite control set model predictive current control, validated experimentally with a rear axle electrical drive unit used in automotive applications. An improved problem formulation is suggested which lowers the computational turnaround time of the solver with approximately $\text{40}\%$ for an horizon length of $N=4$. Apart from the computational requirement aspects, the assessment focuses on inverter efficiency, phase current total demand distortion, and acoustic performance. The proposed solution is evaluated against a standard double proportional and integrator (PI) field-oriented current controller with pulsewidth modulation. It is shown that the proposed solution is feasible, the associated optimization problem at hand can be solved in real time, while exploiting the attractiveness of the proposed improvements. In summary, it is concluded that the inverter efficiency can be improved without deteriorating neither the phase current harmonics nor the acoustic performance. [ABSTRACT FROM AUTHOR]
- Published
- 2020
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10. A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.
- Author
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Kim, Dongkyun, Koo, Kibong, Kim, Yongmi, Lee, Dong Uk, Lee, Jaein, Kwon, Kihun, Choi, Byeongchan, Kim, Hongjung, Ku, Sanghyun, Kim, Jongsam, Oh, Seungwook, Park, Minsu, Im, Dain, Lee, Yongsung, Park, Mingyu, Choi, Jonghyuck, Chun, Junhyun, Jin, Kyowon, Jang, Sungchun, and Song, Jun-Yong
- Subjects
TURNAROUND time ,PERSONAL identification numbers - Abstract
A 1.1-V 6.4-Gb/s/pin 16-Gbit DDR5 is presented in 10-nm class CMOS technology. Various functions and circuits’ techniques are newly adopted to improve performance and power consumption compared with DDR4 SDRAM. First, to realize two times higher speed than DDR4, the injection-locked oscillator (ILO) delay locked loop (DLL) is adopted for the low jitter high-speed performance. The proposed DLL with phase rotator (PR) and ILO allows to minimize the clock tree of DRAM, lowering skew and jitter in the DRAM internal clock path. Second, for the high-speed write operation, DQS gate opening control and write leveling are very important to minimize the turnaround time of DRAM, and thus new sequence and logic for the write-level training are introduced in this article. Third, to maximize the data valid window of read DQs, duty cycle adjustable serialize circuit methods are proposed. Finally, to improve the interface speed, the decision feedback equalization (DFE) and feedforward equalization (FFE) are adopted to Rx and Tx, respectively. By implementing all the items mentioned earlier, the 1.1-V 6.4-Gb/s/pin 16-Gbit DDR5 achieved 6.4-Gb/s/pin performance at 1.05-V $V_{DD}$ , with its power bandwidth efficiency 30% higher than that of DDR4. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
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11. Carrier-Sense Multiple Access With Transmission Acquisition and Channel-Access Prioritization.
- Author
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Carvalho, Marcelo M. and Garcia-Luna-Aceves, J. J.
- Subjects
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WIRELESS LANs , *CARRIER sense multiple access , *TURNAROUND time , *DATA packeting , *LOCAL area networks - Abstract
Carrier-Sense Multiple Access with Transmission Acquisition (CSMA/TA) and channel-access prioritization is presented. CSMA/TA is intended for wireless local area networks of stations endowed with half-duplex transceivers and single antennas. It leverages the small turnaround times of current half-duplex radios to increase the likelihood of having the last transmission from a group of overlapping transmissions succeed, especially if turnaround times are smaller or slightly larger than propagation delays. In CSMA/TA, a station senses the channel before sending a pilot and waits for a short time after sending its pilot before sensing the channel again. If the channel is sensed idle again, the station transmits its data packet. By using appropriate pilot lengths, CSMA/TA allows traffic prioritization at the channel-access level, which supplements traditional output traffic prioritization at stations. It is shown that non-priority CSMA/TA can surpass the performance of such protocols as CSMA, FAMA-PJ, and CSMA/CD if turnaround times are larger than propagation delays, but not too much larger. In addition, it is shown that CSMA/TA can improve traffic prioritization significantly across different traffic classes, under different traffic load proportions, compared to CSMA under the same conditions. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
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12. Deep Neural Network (DNN) Optimized Design of 2.45 GHz CMOS Rectifier With 73.6% Peak Efficiency for RF Energy Harvesting.
- Author
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Lau, Wendy Wee Yee, Ho, Heng Wah, and Siek, Liter
- Subjects
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ENERGY harvesting , *ENERGY consumption , *THRESHOLD voltage , *DC-to-DC converters , *RADIO frequency allocation , *TURNAROUND time - Abstract
This article presents a two-stage rectifier with novel DC-boosted gate bias for RF energy harvesting. The auxiliary gate bias enables rectifier to operate when input amplitude is smaller than its transistor threshold voltage while constraining the positive gate voltage during off state to reduce the reverse leakage current. An automated design optimization methodology using Deep Neural Network (DNN) to maximize efficiency is presented. The DNN is shown to accurately model SPICE simulated response of rectifier. Hence, the design phase turnaround time is minimized with fast prediction of optimized design parameters. The proposed rectifier has been fabricated in 65 nm standard CMOS technology. A maximum power conversion efficiency of 73.6% is measured at 2.45 GHz with input power of −6 dBm. The proposed rectifier has a measured sensitivity of −12 dBm for 1 V output voltage. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
13. Cloud Resource Management With Turnaround Time Driven Auto-Scaling
- Author
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Xiaolong Liu, Shyan-Ming Yuan, Guo-Heng Luo, Hao-Yu Huang, and Paolo Bellavista
- Subjects
Network ,resource management ,big data ,turnaround time ,service management ,Electrical engineering. Electronics. Nuclear engineering ,TK1-9971 - Abstract
Cloud resource management research and techniques have received relevant attention in the last years. In particular, recently numerous studies have focused on determining the relationship between server-side system information and performance experience for reducing resource wastage. However, the genuine experiences of clients cannot be readily understood only by using the collected server-side information. In this paper, a cloud resource management framework with two novel turnaround time driven auto-scaling mechanisms is proposed for ensuring the stability of service performance. In the first mechanism, turnaround time monitors are deployed in the client-side instead of the more traditional server-side, and the information collected outside the server is used for driving a dynamic auto-scaling operation. In the second mechanism, a schedule-based auto scaling preconfiguration maker is designed to test and identify the amount of resources required in the cloud. The reported experimental results demonstrate that using our original framework for cloud resource management, stable service quality can be ensured and, moreover, a certain amount of quality variation can be handled in order to allow the stability of the service performance to be increased.
- Published
- 2017
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14. WIP: Achieving Self-Interference-Free Operation on SDR Platform with Critical TDD Turnaround Time
- Author
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Thijs Havinga, Xianjun Jiao, Muhammad Aslam, Wei Liu, Ingrid Moerman, Chen, L. L., Melodia, T., Tsiropoulou, E. E., Chiasserini, C. F., Bruno, R., Bhattacharjee, S., Frangoudis, P., and Nadendla, V. S. S.
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Computer Science - Networking and Internet Architecture ,Networking and Internet Architecture (cs.NI) ,FOS: Computer and information sciences ,self-interference ,Technology and Engineering ,software defined radio ,receiver sensitivity ,turnaround time ,TDD - Abstract
Software Defined Radio (SDR) platforms are valuable for research and development activities or high-end systems that demand real-time adaptable wireless protocols. While low latency can be achieved using the dedicated digital processing unit of a state-of-the-art SDR platform, its Radio Frequency (RF) front-end often poses a limitation in terms of turnaround time (TT), the time needed for switching from the receiving to the transmitting mode (or vice versa). Zero Intermediate Frequency (ZIF) transceivers are favorable for SDR, but suffer from self-interference even if the device is not currently transmitting. The strict MAC-layer requirements of Time Division Duplex (TDD) protocols like Wi-Fi cannot be achieved using configurable ZIF transceivers without having to compromise receiver sensitivity. Using a novel approach, we show that the TT using the AD9361 RF front-end can be as low as 640 ns, while the self-interference is at the same level as achieved by the conventional TDD mode, which has a TT of at least 55 {\mu}s. As compared to Frequency Division Duplex (FDD) mode, a decrease of receiver noise floor by about 13 dB in the 2.4 GHz band and by about 4.5 dB in the 5 GHz band is achieved., Comment: Accepted by IEEE International Symposium on a World of Wireless, Mobile and Multimedia Networks (WoWMoM 2022) as Work-In-Progress paper
- Published
- 2022
15. Aircraft to Operations Communication Analysis and Architecture for the Future Aviation Environment
- Author
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Saba Al-Rubaye, Nigel Silverthorn, Julia Jiggins, Karim Thomas, Antonios Tsourdos, and Huw Whitworth
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Radio access network ,Aircraft Communications ,business.industry ,Computer science ,Quality of service ,Turnaround time ,RAN ,Game Theory ,Network Slicing ,Key (cryptography) ,Wireless ,Resource allocation ,Resource management ,Aviation ,business ,5G ,Computer network - Abstract
Fifth Generation (5G) systems are envisaged to support a wide range of applications scenarios with varying requirements. 5G architecture includes network slicing abilities which facilitate the partitioning of a single network infrastructure on to multiple logical networks, each tailored to a given use case, providing appropriate isolation and Quality of Service (QoS) characteristics. Radio Access Network (RAN) slicing is key to ensuring appropriate QoS over multiple domains; achieved via the configuration of multiple RAN behaviours over a common pool of radio resources. This Paper proposes a novel solution for efficient resource allocation and assignment among a variety of heterogeneous services, to utilize the resources while ensuring maximum QoS for network services. First, this paper evaluates the effectiveness of different wireless data bearers. Secondly, the paper proposes a novel dynamic resource allocation algorithm for RAN slicing within 5G New Radio (NR) networks utilising cooperative game theory combined with priority-based bargaining. The impact of this work to industry is to provide a new technique for resource allocation that utilizes cooperative bargaining to ensure all network services achieve minimum QoS requirements – while using application priority to reduce data transfer time for key services to facilitate decreased turnaround time at the gate.
- Published
- 2021
16. Partial Order Transactions on Permissioned Blockchains for enhanced Scalability
- Author
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Dayama Pankaj S, Ken Kumar, Akshar Kaul, and Krishnasuri Narayanam
- Subjects
Computer science ,Order (business) ,business.industry ,Scalability ,Hash chain ,State (computer science) ,business ,Turnaround time ,Database transaction ,Throughput (business) ,Computer network ,Block (data storage) - Abstract
Ordering service in a permissioned blockchain platform like Hyperledger Fabric groups the transactions into various blocks. These blocks are linked together via a hash chain to provide immutability. Transactions with less block height get validated before the transactions with more block height. Within a single block, the transactions get validated in the same order they are arranged inside the block. This structure imposes a total order among transactions. This total ordering ensures that all the peer nodes reach the same final state once all the transactions are validated. This total ordering prevents parallel validation of transactions. A given transaction may not be dependent on all the transactions preceding it. However, such a transaction still cannot be validated before completion of validation for all the preceding transactions. This paper presents a blockchain system to support partial ordering among non-dependent transactions. The proposed blockchain system aims to achieve high transaction throughput by enabling parallel transaction validation and reducing the transaction turnaround time by eliminating the need for the transactions to wait for non-dependent predecessor transactions. The proposed blockchain system ensures that all peer nodes reach the same final state even if the order in which they validate the transactions is different.
- Published
- 2021
17. A system for proactive risk assessment of application changes in cloud operations
- Author
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Raghav Batta, Amar Prakash Azad, Michael Nidd, Harshit Kumar, and Larisa Shwartz
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Service (systems architecture) ,Risk analysis (engineering) ,Computer science ,Software deployment ,business.industry ,Reliability (computer networking) ,Cloud computing ,business ,Risk assessment ,Turnaround time ,Due diligence ,Risk management - Abstract
Change is one of the biggest contributors to service outages. With more enterprises migrating their applications to cloud and using automated build and deployment the volume and rate of changes has significantly increased. Furthermore, microservice-based architectures have reduced the turnaround time for changes and increased the dependency between services. All of the above make it impossible for the Site Reliability Engineers (SREs) to use the traditional methods of manual risk assessment for changes. In order to mitigate change-induced service failures and ensure continuous improvement for cloud native services, it is critical to have an automated system for assessing the risk of change deployments. In this paper, we present an AI-based system for proactively assessing the risk associated with deployment of application changes in cloud operations. The risk assessment is accompanied with actionable risk explainability. We discuss the usage of this system in two primary scenarios of automated and manual deployment. In automated deployment scenario, our approach is able to alert SREs on 70 % of problematic changes by blocking only 1.5 % of total changes and recommending human intervention. In manual deployment scenario, our approach recommends the SREs to perform extra due diligence for 2.8 % of total changes to capture 84 % of problematic changes.
- Published
- 2021
18. Backfilling HPC Jobs with a Multimodal-Aware Predictor
- Author
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Kenneth Lamar, Damian Dechev, Jim Brandt, Benjamin A. Allan, Christina Peterson, and Alexander V. Goponenko
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Job scheduler ,Schedule ,ComputingMilieux_THECOMPUTINGPROFESSION ,Operations research ,Computer science ,media_common.quotation_subject ,computer.software_genre ,Turnaround time ,Scheduling (computing) ,Resource (project management) ,Computer cluster ,Quality (business) ,Duration (project management) ,computer ,media_common - Abstract
Job scheduling aims to minimize the turnaround time on the submitted jobs while catering to the resource constraints of High Performance Computing (HPC) systems. The challenge with scheduling is that it must honor job requirements and priorities while actual job run times are unknown. Although approaches have been proposed that use classification techniques or machine learning to predict job run times for scheduling purposes, these approaches do not provide a technique for reducing underprediction, which has a negative impact on scheduling quality. A common cause of underprediction is that the distribution of the duration for a job class is multimodal, causing the average job duration to fall below the expected duration of longer jobs. In this work, we propose the Top Percent predictor, which uses a hierarchical classification scheme to provide better accuracy for job run time predictions than the user-requested time. Our predictor addresses multimodal job distributions by making a prediction that is higher than a specified percentage of the observed job run times. We integrate the Top Percent predictor into scheduling algorithms and evaluate the performance using schedule quality metrics found in literature. To accommodate the user policies of HPC systems, we propose priority metrics that account for job flow time, job resource requirements, and job priority. The experiments demonstrate that the Top Percent predictor outperforms the related approaches when evaluated using our proposed priority metrics.
- Published
- 2021
19. Proteus: Distributed machine learning task scheduling based on Lyapunov optimization
- Author
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Yongan Xiang, Bin Shi, and Chongle Zhang
- Subjects
Schedule ,Job shop scheduling ,business.industry ,Computer science ,Cloud computing ,Lyapunov optimization ,Machine learning ,computer.software_genre ,Turnaround time ,Scheduling (computing) ,Task (computing) ,Artificial intelligence ,business ,Resource management (computing) ,computer - Abstract
With the prevalence of machine learning applications, an increasing number of machine learning tasks is transplanted into cloud computing platform. The cloud for machine learning consists of heterogeneous resources such as GPUs, CPUs, memory, etc, which brings challenges for resource management. So, how to schedule machine learning tasks and allocate appropriate GPU resources for computing, so that the cluster can maximize the use of resources and reduce task computing time has become a concern in the industry and academia. This paper proposes a scheduling strategy named Proteus, which is based on Lyapunov optimization. Through the Proteus, we can make our tasks have a minimum turnaround time in a long time sequence, which is the time from the submission of the task to the completion of the task. By performing a comprehensive analysis, we implement the scheduling algorithm and conducts several simulation experiments. The experimental result shows that our scheduling strategy can achieve significant results in most task scheduling environments, reducing the turnaround time of tasks to 40%–50% of the original. This shows that the Proteus can provide higher resource utilization and performance of cloud clusters and reduce task turnaround time.
- Published
- 2021
20. Machine-Learning based TCAD Optimization Method for Next Generation BCD Process Development
- Author
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Dawon Jung, Dae Sin Kim, Kyu-ok Lee, Yongwoo Jeon, Yong-Don Kim, UiHui Kwon, Jaehyun Yoo, Kwangtae Kim, Oh-Kyum Kwon, Jeahyun Jung, Junhyuk Kim, and Jisu Ryu
- Subjects
010302 applied physics ,Computer science ,Process development ,020208 electrical & electronic engineering ,02 engineering and technology ,Integrated circuit ,01 natural sciences ,Turnaround time ,Process conditions ,law.invention ,Ion implantation ,law ,0103 physical sciences ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,Optimization methods - Abstract
An automatic optimization methodology based on AI algorithm is proposed to achieve multi-targeting of various devices in 0.13 μm next BCD process development. The optimized process conditions are simultaneously provided with satisfying various ET-specs of the BCD devices from our method and TCAD analysis. The method has practically been applied to well ion implantation processes shared with seven different devices, and its targeting rate of 87% has been verified through silicon evaluation. Its turnaround time (TAT) is reduced by 90% compared to conventional procedure.
- Published
- 2021
21. Software Reuse Management for better efficiency and turnaround time
- Author
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Anandaraj Rangasamy, Vanishree Nagaraj, and Karthikrajan Nandhakumar
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AUTOSAR ,business.industry ,Computer science ,Strategic business unit ,Time to market ,Component (UML) ,New product development ,Reuse ,Business model ,business ,Turnaround time ,Manufacturing engineering - Abstract
In this ever growing, competitive market with Technological advancements Reuse management plays an important role in reducing the time to market and optimizing the R&D to sales ratio. It’s now clear that to achieve better software, more quickly and at lower cost, we need a design process that is based on systematic software reuse In any R&D engineering center like ours, the reuse management strives to launch competitive, focus on innovative products with high profiting business models in the shortest lead time possible. In this paper, a novel approach is proposed that embarks the journey of reuse component identification wrt,•Common across customer projects,•Common across product lines•Common across Business unit levelThis method is derived from both AutoSAR and Non AutoSAR project architecture. This method has been piloted in our Engineering Center and has proven to be a very method for computing (evaluating) and thereby improving the reuse. This in turn minimizes effort and cost in product development and adapting market strategy in its business models. Keywords-Feature, Reuse component identification, Reuse Index calculation, Market estimation, Value addition
- Published
- 2021
22. Autotuning LSTM for Accelerated Execution on Edge
- Author
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Ankur Deshwal, Ujjawal Chugh, Arnab Mitra, Seungwon Lee, Kavitha T. Madhu, Joon-Ho Song, and Aditi Saluja
- Subjects
Speedup ,Computer engineering ,Edge device ,Computer science ,Computation ,Hyperparameter optimization ,Applications of artificial intelligence ,Enhanced Data Rates for GSM Evolution ,Layer (object-oriented design) ,Turnaround time - Abstract
Deployment of Deep Neural Networks (DNNs) on edge devices is highly desirable to address user privacy concerns and minimize the turnaround time of AI applications. However, the execution of DNN models on a battery-operated device requires a highly optimized implementation specific to the target hardware. Moreover, as different layers of a DNN exhibit distinct computation and memory characteristics, it is imperative to optimize each layer separately. This is in contrast to the widely deployed library-based approach where all the configurations of DNN operations share the same implementation. In this paper, we address this issue by auto-tuning the implementation of Long Short Term Memory (LSTM) operations which are widely used in sequence based AI applications. To exhaustively search through the space of optimizations and its parameters, we develop a high-level autotuning framework based on Halide. We use grid search to find the parameters that lead to minimum runtime and further present TPE based search method to find the near-optimal runtime in a limited number of trials. We observe 2.2× —3.1× speedup in execution time for LSTM layers used in widely deployed GNMT and DeepSpeech2 models.
- Published
- 2021
23. A Petri Net-Based Heuristic Algorithm for Short-Term Vehicle Scheduling in a Vehicle Inspection System
- Author
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Hanhan Cheng, Pei Chen, Naiqi Wu, Linjian Yang, Xiangmo Zhao, and Yisheng An
- Subjects
0209 industrial biotechnology ,General Computer Science ,Job shop scheduling ,resource-oriented petri net ,Computer science ,General Engineering ,02 engineering and technology ,Petri net ,Turnaround time ,Reliability engineering ,Scheduling (computing) ,020901 industrial engineering & automation ,vehicle test turnaround time ,0202 electrical engineering, electronic engineering, information engineering ,heuristic algorithm ,020201 artificial intelligence & image processing ,General Materials Science ,lcsh:Electrical engineering. Electronics. Nuclear engineering ,Queue ,Vehicle inspection system ,short-term vehicle scheduling ,lcsh:TK1-9971 ,Vehicle inspection - Abstract
Vehicle inspection systems (VIS) have been extensively used by automobile manufacturers, maintenance companies, and the traffic administrative departments for the inspection of safety, reliability, and other indicators of both newly produced and in-used vehicles. How to increase their productivity by effectively operating such systems is an interesting and crucial problem. Because of the space limitation of testing field in such a system, a vehicle must complete pre-set inspection items at multiple stations in sequence. Hence, it is very challenging to sequence the vehicles to be tested to shorten the unnecessary waiting time for vehicle testing. This paper investigates the vehicle scheduling problem of such systems, where the time for vehicle movement in the system can be ignored. The system is modeled by resource-oriented Petri net, a graphical and mathematical modeling tool. Based on the model, this work analyzes the testing cycle time and develops a heuristic algorithm to efficiently solve the vehicle scheduling problem in such a system. For the first time, a heuristic algorithm for generating an optimal vehicle queue for testing is proposed. Industrial examples are used to illustrate the proposed algorithm and results show that a significant reduction in total test turnaround time can be obtained in comparison with the existing methods.
- Published
- 2019
24. Two-Level Scheduling Technology For Heterogeneous Clusters Using Analytical Hierarchy Processes
- Author
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Xiaoyuan Zhang, Jianhua Gu, and Tianhai Zhao
- Subjects
Job scheduler ,Computer science ,Distributed computing ,Two-level scheduling ,Analytical hierarchy ,Analytic hierarchy process ,Communications system ,computer.software_genre ,Throughput (business) ,Turnaround time ,computer ,Scheduling (computing) - Abstract
The cluster system presents multi-level and complex heterogeneous features with GPUs computing. Job scheduling technology determines computing resource utilization and throughput of the cluster system. On the basis of heterogeneous cluster system, the two-level scheduling technology is proposed in this paper. In the first level, a job priority scheduling algorithm based on user value is designed at the cluster level using analytical hierarchy processes. The second level of scheduling is to act on the computing nodes that contain GPUs, and design a scheduling algorithm based on GPU sharing policy that manages GPU jobs in a more fine-grained manner. Through experiments, it shows that the job priority scheduling algorithm based on user value can ensure that jobs with high user value are executed first, and fairness is guaranteed. The scheduling algorithm based on GPU sharing technology can significantly improve the utilization of GPU and video memory, reducing the average waiting time of jobs by 55.54% and the average turnaround time of jobs by 28.83%.
- Published
- 2021
25. Numerical and Simulation Verification for Optimal Server Allocation in Edge Computing
- Author
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Chigozie Asikaburu, Jiacheng Shang, Ning Wang, and Dawei Li
- Subjects
Queueing theory ,business.industry ,Heuristic (computer science) ,Computer science ,Server ,Distributed computing ,CloudSim ,Cloud computing ,Enhanced Data Rates for GSM Evolution ,business ,Computer Science::Operating Systems ,Turnaround time ,Edge computing - Abstract
In this paper, we consider the server allocation problem in edge computing. We consider a system model where there are a number of areas or locations, each of which has an associated Base Station (BS), where we can deploy an edge cloud with multiple servers. Each edge cloud will process application requests received at the corresponding BS from users in the corresponding area. The system manager/operator has a budget to deploy a given number of servers to the BSs. Our goal is to come up with a server allocation plan, i.e., how many servers to deploy at each of the BSs, such that the overall average turnaround time of application requests generated by all the users is minimized. In order to achieve the optimal solution for the problem, we resort to queueing theory and model each edge cloud as an M/M/c queue. Analysis on the problem motivates a Largest Weighted Reduction Time First (LWRTF) algorithm to assign servers to edge clouds. Numerical comparisons among various algorithms verify that Algorithm LWRTF has near-optimal performances in terms of minimizing the average turnaround time. Simulation results using the CloudSim Plus simulation tool also verify that Algorithm LWRTF achieves better performances compared to other reasonably designed heuristic algorithms.
- Published
- 2021
26. Towards Software-Centric Listen-Before-Talk on Software-Defined Radios
- Author
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Anatolij Zubow, Falko Dressler, and Sebastian Brauer
- Subjects
Protocol stack ,Flexibility (engineering) ,Software ,SIMPLE (military communications protocol) ,Computer architecture ,Computer science ,business.industry ,Key (cryptography) ,Software-defined radio ,business ,Host (network) ,Turnaround time - Abstract
Listen-Before-Talk (LBT) is an essential function of many MAC protocols and a key mechanism of sharing spectrum in an uncoordinated manner. However, this simple but effective concept remains a major challenge for Software-Defined Radios (SDRs). If performing the protocol stack on a host PC, due to their structure, SDRs have inherent latencies built in. These latencies increase their reaction time, the so-called turnaround time, significantly, compared to their conventional radio counterparts. Unfortunately, this means that they cannot comply with the LBT channel access procedures used in modern protocols like IEEE 802.11 or LTE Licensed-Assisted Access (LTE-LAA). Given the flexibility and rapid-prototyping capabilities of SDRs, these protocols could clearly benefit from such SDR-based implementations. In this paper, we fill this gap and present a design approach for SDRs supporting LBT. We particularly focus on the rather complicated timing issues. As a proof-of-concept, we showcase our LBT-enabled implementation of the srsLTE software stack for LTE.
- Published
- 2021
27. Development of Approaches to Assessing the Actual Technical Condition of Steam Turbines Based on Reliability Indicators
- Author
-
Valentina S. Lunenko, Mahsud M. Sultanov, and Maksim S. Ivanitckii
- Subjects
Electricity generation ,Steam turbine ,Computer science ,food and beverages ,Thermal power station ,Failure rate ,State (computer science) ,Residual ,Turnaround time ,Reliability (statistics) ,Reliability engineering - Abstract
The article presents the results of analyzing the failure statistics of the main components of steam turbines of thermal power plants. Based on the results of the analysis established that the complexity of technological processes, taking into account turnaround time, failure rate, the production cycle of the equipment residual life allows to develop approaches to assessing the health of each element with the aim of obtaining reliable and representative sample of failure statistics to reliability assessment of steam turbine plants. It is shown that the statistics of finding equipment in a state of partial failure is an important factor for improving the overall reliability of equipment. The results obtained can be used to create predictive models that provide approaches to prolonging the operational state of elements of steam turbine installations, as well as for implementing projects of digital energy systems that include subsystems for monitoring and diagnostics of power equipment of thermal power plants.
- Published
- 2021
28. Workflow and Process Automation of Residential DER Interconnection Review
- Author
-
Esa Aleksi Paaso, Beata Okruta, and Nina Selak
- Subjects
Interconnection ,Engineering management ,Workflow ,Smart grid ,business.industry ,Process (engineering) ,Computer science ,Distributed generation ,business ,Process automation system ,Automation ,Turnaround time - Abstract
Distributed Energy Resources (DER) are revolutionizing how utilities plan and operate the grid, which ultimately influences the customer experience. Partially driven by increasing federal and state incentives for DERs, there is an increased interest to integrate solar generation facilities with the grid. To put this into perspective, interconnection applications in ComEd's territory increased more than 1,500% in the last three years and the accelerating trend continues. Most interconnection applications are for solar facilities that are less than 25kW in capacity (“Level 1” applications). The potential adverse impacts of each interconnection needs to be evaluated. Traditionally, a Level 1 technical screening is a manual process that involves reviewing the application against predetermined criteria set forth in the Illinois Administrative Code. ComEd has developed and deployed innovative solutions to automate such reviews by integrating data from multiple legacy ComEd systems and analyzing Level 1 applications to verify, that the applications meet the criteria to pass the technical screens. The automated technical screening process for most Level 1 application has facilitated improved management of complex utility scale commercial and industrial interconnection applications. This automation initiative has also enhanced customer service by significantly decreasing interconnection application turnaround time and ensuring a premier customer experience.
- Published
- 2021
29. Secure Blockchain for Admission Processing in Educational Institutions
- Author
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Rida Javed Kutty and Nazura Javed
- Subjects
Blockchain ,Smart contract ,Process (engineering) ,Computer science ,Compromise ,media_common.quotation_subject ,05 social sciences ,050301 education ,02 engineering and technology ,Computer security ,computer.software_genre ,Turnaround time ,Transparency (behavior) ,020204 information systems ,0202 electrical engineering, electronic engineering, information engineering ,Business logic ,0503 education ,computer ,media_common - Abstract
Blockchain technology with its secure mechanism of maintaining data and transactions in shared, immutable, distributed ledgers has become very relevant today and is increasingly used for financial applications. This paper proposes the use of consortium blockchain and smart contracts for secure, transparent and automated processing of student applications received by educational institutions. The students applying for admissions in educational institutions need assurance of a safe, secure and transparent platform that does not compromise their privacy. On the other hand, educational institutions too need assurance about the authenticity of the documents and the applicant. The use of consortium blockchain and smart contracts incorporating business logic for validating, verifying and filtering of valid applications provides a safe and secure platform for processing student applications. This paper looks at blockchain application beyond finance and explains how the student registration and admission process can be made safe and secure for all stakeholders. It promotes a seamless mechanism with reduced turnaround time and increased security and transparency.
- Published
- 2021
30. Real-Time Task Scheduling in Fog-Cloud Computing Framework for IoT Applications: A Fuzzy Logic based Approach
- Author
-
Hala S. Ali, Sajal K. Das, Rashmi Ranjan Rout, and Priyanka Parimi
- Subjects
Job shop scheduling ,business.industry ,Computer science ,Distributed computing ,020208 electrical & electronic engineering ,Bandwidth (signal processing) ,020206 networking & telecommunications ,Cloud computing ,02 engineering and technology ,Fuzzy logic ,Turnaround time ,Scheduling (computing) ,Task (computing) ,0202 electrical engineering, electronic engineering, information engineering ,Task analysis ,business - Abstract
As an extension of the cloud, a fog computing environment facilitates the deployment of Internet of Things (IoT) applications by shifting the computing, storage and networking services closer to the IoT devices, thus satisfying the delay and response time requirements. This paper aims to improve the overall task execution efficiency of IoT applications by appropriately selecting customized real-time tasks for execution at the fog layer. Specifically, we propose a fuzzy logic based task scheduling algorithm to divide the tasks between the fog and cloud layers in a fog-cloud computing framework. The algorithm selects appropriate processing units to execute the submitted tasks in the fog layer with heterogeneous resources, by exploiting the task requirements (e.g., computation, storage, bandwidth) and their constraints (e.g., deadline, data size). Simulation experiments demonstrate the efficacy of the proposed algorithm and its superior performance as compared to other existing algorithms in terms of success ratio of the tasks, makespan, average turnaround time, and delay rate.
- Published
- 2021
31. Performance Analysis and Comparison Among Different Task Scheduling Algorithms in Cloud Computing
- Author
-
Md. Tanvir Alam Siddique, Tanvir Ahammad, and Selina Sharmin
- Subjects
Job shop scheduling ,business.industry ,Computer science ,Distributed computing ,CloudSim ,Task analysis ,Cloud computing ,Load balancing (computing) ,business ,Turnaround time ,Task (project management) ,Scheduling (computing) - Abstract
In the field of cloud computing, efficient task scheduling plays a vital role. Cloud computing is an on-demand service where resources are shared virtually by the users to complete their tasks. The main concept of task scheduling is to execute the tasks in such an order that can enhance the performance with full resource utilization and minimum loss. Already a lot of scheduling algorithm exists targeting to various goals like reducing execution time, cost, makespan and increase resource utilization, load balancing, etc. In this work, we have mainly carried out the performance analysis and comparison among various well-known task scheduling algorithms. The algorithms are examined and implemented in a well-known cloud simulator (CloudSim) to observe their performances by varying different parameters. Finally, the performance metrics like makespan, waiting time, turnaround time, throughput, and load balancing are observed by plotting the results graphically. Along with the comparative analysis, this work also assists one to identify a better scheduling algorithm based on different scheduling constraints and criteria.
- Published
- 2020
32. MegaPath-Nano: Accurate Compositional Analysis and Drug-level Antimicrobial Resistance Detection Software for Oxford Nanopore Long-read Metagenomics
- Author
-
Yan Xin, Patrick C. Y. Woo, Henry C. M. Leung, Tak-Wah Lam, Ruibang Luo, Wui Wang Lui, Jade L. L. Teng, and Amy W. S. Leung
- Subjects
Profiling (computer programming) ,0303 health sciences ,030306 microbiology ,Computer science ,business.industry ,Genomics ,computer.software_genre ,Turnaround time ,03 medical and health sciences ,Software ,Metagenomics ,Minion ,RefSeq ,Data mining ,Nanopore sequencing ,business ,computer ,030304 developmental biology - Abstract
Accurate and sensitive taxonomic profiling is essential for any metagenomic analysis to reveal microbial community structure and for potential functional prediction. Antimicrobial resistance (AMR) detection is also a critical task in the clinical diagnosis of infection and antimicrobial therapy. By incorporating Oxford Nanopore Technologies (ONT) sequencing, users benefit from the high-confidence alignment of long reads for taxonomic classification, even among bacteria with similar genomes. Portable ONT devices, such as VolTRAX with MinION, allow short turnaround time for detection and can be used in a lightweight laboratory setting. However, error-prone ONT sequencing reads are still challenging for existing software for accurate taxonomic classification of microbes and detection of AMR down to the drug level. In this paper, we present MegaPath-Nano, the successor to NGS-based MegaPath. It is a high-precision compositional analysis software with drug-level AMR detection for ONT metagenomic sequencing data. MegaPath-Nano performs 1) thorough multi-level filtering against decoy and human reads while removing noisy alignments, 2) alignment-based taxonomic classification with RefSeq down to strain-level, with an alignment-reassignment algorithm to tackle the challenge of non-unique alignments, based on global alignment distribution, and 3) comprehensive downstream drug-level AMR detection, integrating five AMR databases. In our benchmarks using the Zymo metagenomic dataset, MegaPath-Nano performed better than other existing software for taxonomic classification. We also sequenced five real patient isolates using MinION to benchmark its performance of AMR detection. MegaPath-Nano was the most accurate and provided the most comprehensive output at both the drug and class level of AMR prediction against other state-of-the-art software. MegaPath-Nano is open-source and available at https://github.com/HKU-BAL/MegaPath-Nano.
- Published
- 2020
33. Design of AI-Enhanced Drug Lead Optimization Workflow for HPC and Cloud
- Author
-
Giacomo Domeniconi, Leili Zhang, Chih-Chieh Yang, and Guojing Cong
- Subjects
0303 health sciences ,010304 chemical physics ,Computer science ,business.industry ,Drug discovery ,Distributed computing ,Big data ,Process (computing) ,Cloud computing ,01 natural sciences ,Autoencoder ,Turnaround time ,03 medical and health sciences ,Workflow ,0103 physical sciences ,Cluster analysis ,business ,030304 developmental biology - Abstract
Drug discovery is a costly process of searching for new candidate medications. Among its various stages, lead optimization easily consumes more than half of the pre-clinical budget. We propose an automated lead optimization workflow that uses data mining methods in components such as execution of molecular simulations, feature extraction, and clustering with convolutional variational autoencoder. The end-to-end execution produces protein-ligand binding affinity of atoms in the lead molecule which serves as metrics for identifying modifiable atoms. In contrast to known methods, our method provides new hints for drug modification hotspots which can be used to improve drug efficacy. Our workflow can potentially reduce the lead optimization turnaround time from months/years to several days compared with the conventional labor-intensive process and thus will become a valuable tool for medical researchers.
- Published
- 2020
34. Scheduling Optimization of real-time IOT system based on RNN
- Author
-
Chunyuan Zhang, Shenling Liu, and Yujiao Chen
- Subjects
Ubiquitous computing ,Computer science ,business.industry ,Quality of service ,Distributed computing ,020206 networking & telecommunications ,Cloud computing ,02 engineering and technology ,Turnaround time ,Scheduling (computing) ,Recurrent neural network ,0202 electrical engineering, electronic engineering, information engineering ,020201 artificial intelligence & image processing ,business ,Wireless sensor network ,Queue - Abstract
Ubiquitous computation, which promoted by Rapid development of Wireless Sensor Network (WSN) technologies cuts across many areas of modern day living, Internet of Things has been identified as one of Network Infrastructure in the next generation of application domains. An architecture based on cloud computing at the center, which contribute to highly flexibility and scalablity, is an extensively used scheme to construct IOT applications. With growing number of intelligent terminals and third part application accessing on the platform, the Qos problem caused by the large-scale concurrent access rise to the surface. To address this question, a self-adaption Multi-level Feedback Queue Scheduling policy, used to reduce mean turnaround time and complexity of scheduling, based on Recurrent Neural Network (RNN) is presented in this paper. Feature parameters of queues and tasks are used as input of network, the calculated parameters are exported to optimize queue parameters continuously. This research implement a prototype of this scheme. According To demonstrate the efficiency, this thesis give performance results from our prototype and other scheduling policy.
- Published
- 2020
35. Multi-Layer Scheduling Optimization for Intelligent Mobility of Maritime Operation
- Author
-
Jayaraman Vasundhara, Hai-Yan Xu, Xiuju Fu, Deqing Zhai, Xiao Feng Yin, and Wanbing Zhang
- Subjects
050210 logistics & transportation ,Computer science ,0502 economics and business ,05 social sciences ,Real-time computing ,010103 numerical & computational mathematics ,Performance indicator ,0101 mathematics ,01 natural sciences ,Turnaround time ,Multi layer ,Scheduling (computing) - Abstract
In this study, multi-layer scheduling optimization algorithms are proposed and validated based on historical vessel operation data in maritime terminals. The most relevant KPIs are average wait time, average turnaround time and berth occupancy rate presented in this study. Through the proposed optimization algorithms, the results shown that average wait time and turnaround time are significantly reduced with increasing of randomness threshold, which is a threshold to allow reschedules to buffer terminals. The average wait time and turnaround time are shortened by around 27.30 hrs (by 39.06%) and 39.41 hrs (by 27.18%), respectively. The berth occupancy rate of less utilized buffer terminals is also improved from 21.39% to 38.35%.
- Published
- 2020
36. Improved Round Robin Scheduling Algorithm With Varying Time Quantum
- Author
-
Fiad Alaa, Bendoukha Hayat, and Mekkakia Maaza Zoulikha
- Subjects
Job shop scheduling ,Computer science ,business.industry ,Distributed computing ,Cloud computing ,Round-robin scheduling ,computer.software_genre ,Turnaround time ,Scheduling (computing) ,Task (computing) ,Virtual machine ,Task analysis ,business ,computer - Abstract
Cloud computing is a distributed computing model; which refers to manipulating, configuring, and accessing the applications online. It offers online data storage, infrastructure and application. Task scheduling is one of the most important issues in cloud environment, such as the tasks must be affected to the appropriate virtual machines considering different factors at the same time, which leads to considering the task scheduling problem an NP-complete problem. This article presents an improved ROUND ROBIN (RR) CPU scheduling algorithm with varying time quantum. The appropriate algorithm proven better than traditional RR and IRRVQ algorithms. The results show that the waiting time and turnaround time have been reduced in the proposed approach compared to traditional RR and IRRVQ
- Published
- 2020
37. Non-contiguous processor allocation in the mesh-connected multicomputers using compaction.
- Author
-
Bani-Mohammad, Saad, Ababneh, Ismail, and Yassen, Mohammad
- Abstract
In non-contiguous allocation, a job request can be split into smaller parts that are allocated possibly non-adjacent free sub-meshes rather than always waiting until a single sub-mesh of the requested size and shape is available. Lifting the contiguity condition is expected to reduce processor fragmentation and increase system utilization. However, the distances traversed by messages can be long, and as a result the communication overhead, especially contention, is increased. The extra communication overhead depends on how the allocation request is partitioned and assigned to free sub-meshes. In this paper, a new non-contiguous processor allocation strategy, referred to as A Compacting Non-Contiguous Processor Allocation Strategy (CNCPA), is suggested for the 2D mesh networks. In the proposed strategy, a single job is compacting into more than one free location within the allocated processors, where the remaining available processors (free processors) form a large sub-mesh in the system. To evaluate the performance improvement achieved by the proposed strategy and compare it against well-known existing non-contiguous allocation strategies, we conduct extensive simulation experiments under the assumption of wormhole routing and the one-to-all and near neighbor communication patterns. The results show that the proposed strategy can eliminate both the internal and external fragmentation and reduce the communication overhead and hence improve performance in terms of job turnaround time and system utilization. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
- Full Text
- View/download PDF
38. A dynamic load balancing strategy with adaptive threshold based approach.
- Author
-
Alam, Taj and Raza, Zahid
- Abstract
To meet the objective of minimizing the job execution time, parallel computing has to deal with a lot of issues which crop up while working with parallel code. These issues can result in bottleneck and restrict the behavior of parallel program in attaining an aforesaid speedup as suggested by Amdahl Gene. The most problematic issue that crops up is the distribution of workload in both the categories of parallel system viz. homogeneous and heterogeneous systems. This situation demands an effective load balancing strategy to be in place in order to ensure a uniform distribution of load across the board. The scheduling ‘m’ jobs to ‘n’ resources with the objective to optimize the QoS parameters while balancing the load has been proven to be NP-hard problem. Therefore, a heuristic approach can be used to design an effective load balancing strategy. In this paper, a centralized dynamic load balancing strategy using adaptive thresholds has been proposed for a parallel system consisting of multiprocessors. The scheduler continuously monitors the load on the system and takes corrective measures as the load changes. The threshold values considered are adaptive in nature and are readjusted to suite the changing load on the system. Therefore, the scheduler always ensures a uniform distribution of the load on the processing elements with dynamic load environment. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
- Full Text
- View/download PDF
39. Level based task duplication strategy to minimize the job turnaround time.
- Author
-
Sajid, Mohammad and Raza, Zahid
- Abstract
One of the major addressable issues in Parallel and Distributed Systems is scheduling i.e. mapping of tasks on processing nodes in order to optimize the QoS parameters. Task Duplication is an effective approach to minimize turnaround time and communication overheads and to improve system robustness. Task duplication effectively ensures redundantly execution of some task on which some other task critically depends. The task scheduling with duplication and without duplication is known to be an NP-complete problem. This work proposes a static scheduling based on module dependence degree and task duplication in order to minimize the turnaround time of the job. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
- Full Text
- View/download PDF
40. A Novel Reinforcement-Learning-Based Approach to Scientific Workflow Scheduling
- Author
-
Peng Chen, Yunni Xia, Lei Wu, and Hang Liu
- Subjects
021110 strategic, defence & security studies ,Correlated equilibrium ,business.industry ,Computer science ,Quality of service ,Distributed computing ,0211 other engineering and technologies ,Cloud computing ,02 engineering and technology ,Turnaround time ,Scheduling (computing) ,Workflow ,0202 electrical engineering, electronic engineering, information engineering ,Workflow scheduling ,Reinforcement learning ,020201 artificial intelligence & image processing ,business - Abstract
Recently, the Cloud Computing paradigm is becoming increasingly popular in supporting large-scale and complex workflow applications. The workflow scheduling problem, which refers to finding the most suitable resource for each task of the workflow to meet user defined quality of service (QoS), attracts considerable research attention. Multi-objective optimization algorithms in workflow scheduling have many limitations, e.g., the encoding schemes in most existing heuristic-based scheduling algorithms require prior experts' knowledge and thus they can be ineffective when scheduling workflows upon dynamic cloud infrastructures with real-time. To address this problem, we propose a novel Reinforcement-Learning-Based algorithm to multi-workflow scheduling over IaaS clouds. The proposed algorithm aims at optimizing make-span and dwell time and is to achieve a unique set of correlated equilibrium solution. In the experiment, our algorithm is evaluated for famous scientific workflow templates and real-world industrial IaaS cloud platforms by a simulation process and we compare our algorithm to the current state-of-the-art heuristic algorithms, e.g., NSGA-II, MOPSO, GTBGA. The result shows that our algorithm performs better than compared algorithm.
- Published
- 2020
41. Physical Verification of Panel-Level Packaging Designs Utilizing Die Drift Patterning Technology
- Author
-
Tarek Ramadan and Sean Wang
- Subjects
Interconnection ,Design rule checking ,Wafer-scale integration ,Physical verification ,business.industry ,Computer science ,Integrated circuit ,Turnaround time ,Die (integrated circuit) ,law.invention ,Chip-scale package ,law ,Embedded system ,business - Abstract
Panel-level packaging such as fan-out wafer-level packaging (FOWLP) has been a promising technology for a number of years now, primarily as a means of packaging semiconductor devices containing interconnect densities that exceed the capabilities of standard wafer-level chipscale packaging (WLCSP). One of the historical barriers to the broad adoption of panel-level packaging is the yield loss associated with “die drift”-die that shift from their designed nominal positions within each package during the manufacturing process. To break through this barrier, we introduce a novel die drift patterning technology that recognizes and adjusts for die drift, making “design during manufacturing” feasible and practical. However, both panel-level packaging and the die drift patterning methodology introduce physical verification challenges that are unfamiliar to most package designers. Panel-level packaging uses a GDSII or OASIS format for the package design, similar to integrated circuit (IC) design databases. Although design rule checking (DRC) is normally run on each individual unit GDSII file, the Die drift patterning process must also be simulated on a complete panel as one overall GDSII mask. This panel GDSII mask includes unique characteristics, with typically thousands of units requiring concurrent verification. The process is substantially more challenging than a classic unit design, where many repetitive GDSII cells exist within a hierarchy that can be used by the verification tools to improve runtimes. Deca collaborated with Mentor, a Siemens business (Mentor) to optimize physical verification for this panel GDSII mask verification. Together, they worked to identify operational impediments and implement optimizations to the verification toolsuite that enabled the platform to support verification of the die drift patterning technology for M-Series fan-out panel level packaging, while also achieving a reasonable turnaround time (TAT) for panel verification. This optimization utilizes both CPU scaling capabilities and a novel computational approach that accounts for the unique characteristics of a die drift patterning panel-level GDSII mask.
- Published
- 2020
42. In-Flight Entertainment Datalink Analysis and Simulation
- Author
-
Ivan Petrunin, Shahid Ayub, Saba Al-Rubaye, Gary Dent, Gareth Stapylton, and Antonios Tsourdos
- Subjects
Airport connectivity ,In-flight entertainment ,business.industry ,Computer science ,Quality of service ,Riverbed modeler ,Terabyte ,Turnaround time ,Datalink ,Software deployment ,Network performance ,Wireless ,Telecommunications ,business ,Wi-Fi ,Data transmission - Abstract
In-Flight Entertainment (IFE) datalink is one of the airport connectivity areas, where efforts are being made by different stakeholders to improve and update the entertainment services offered to the passengers. An important objective of IFE datalink is to increase the flight operation efficiency by managing IFE data transfer within turnaround time which is about 45 minutes. With the rapid advancements and innovation in multimedia applications and services, the IFE data size in the future will turn into terabytes, therefore, this transfer requires a multi-Gbps datalink in order to be completed within expected turnaround time. This paper focuses on simulation of IFE datalink communication scenario at an airport surface using Wi-Fi (802.11ac) technology, provides rules and guidelines on suitability of wireless datalinks for IFE update at the airports, studies QoS requirements, and performs optimization. Several aspects of the IFE datalink selection and deployment have been considered, such as airport operational areas, airport layouts, radio frequency, and data congestion before conducting a capacity and coverage analysis.
- Published
- 2020
43. Developing a framework to improve the accuracy of point-of-care testing for healthcare applications
- Author
-
Kushal Rashmikant Dalal
- Subjects
Computer science ,business.industry ,Process (engineering) ,Point-of-care testing ,Context (language use) ,Emergency department ,medicine.disease ,Turnaround time ,Test (assessment) ,Health care ,medicine ,Medical emergency ,business ,Point of care - Abstract
Point-of-Care Test (POCT) is considered as the diagnostic test which is administrated in the outside of the central laboratory ator near the patient location. Therefore, it can be stated that the use of POCT devices in the department of emergency represents a significant benefit to the management of the patient. It can be able to give proper governance to credible policy, safe practice, and effective process performance by the healthcare clinics. The major contribution of the POCT is it can give a huge improvement over the test result in the context of turnaround time. Here this research paper considers the process of development framework of POCT in the emergency department (ED). Moreover, the challenges faced by the clinical staff during the usage of previous POCT and the implementation process are also discussed to give a clear clarification about the essentiality of the developed framework of POCT.
- Published
- 2020
44. Development of Automated Detection and Wireless Reporting for a Handheld Point-of-Care Test
- Author
-
Cindy Baumann, Toomas Rang, Tamas Pardy, and Massimo Leonardo Filograno
- Subjects
Medical diagnostic ,business.industry ,Computer science ,Point-of-care testing ,010102 general mathematics ,STRIPS ,01 natural sciences ,Turnaround time ,law.invention ,03 medical and health sciences ,Microcontroller ,0302 clinical medicine ,law ,Wireless ,030212 general & internal medicine ,0101 mathematics ,business ,MATLAB ,Mobile device ,computer ,Computer hardware ,computer.programming_language - Abstract
Second-generation rapid diagnostic tests, e.g. Lab-on-a-Chip (LoC) molecular diagnostics can help decentralize medical diagnostics for infectious diseases and provide far wider coverage than existing methods. Furthermore, they can provide results far more quickly, enabling early diagnosis and prevention of epidemics. However, to ensure a short turnaround time in testing, a compact, ideally low-cost, automated readout method is required. Preferably, the readout should also have integrated means of communication for automatic report of the results. We demonstrate a readout solution based on an ESP12F microcontroller board to read results from a LoC device demonstrated in our previous works. The readout solution relies on an LED-photodiode setup to read the results of immunochromatographic test strips. We evaluated the device by comparing readouts of positive and negative strips. During the evaluation, the device prototype was run from batteries and transmitted results via Wi-Fi to a PC, where a MATLAB application processed, displayed and saved results.
- Published
- 2020
45. Lambdata: Optimizing Serverless Computing by Making Data Intents Explicit
- Author
-
Yang Tang and Junfeng Yang
- Subjects
Schedule ,Speedup ,Computer science ,business.industry ,Distributed computing ,Cloud computing ,02 engineering and technology ,Turnaround time ,Scheduling (computing) ,020204 information systems ,0202 electrical engineering, electronic engineering, information engineering ,Key (cryptography) ,business ,Cloud storage - Abstract
Serverless computing emerges as a new paradigm to build cloud applications, in which developers write small functions that react to cloud infrastructure events, and cloud providers maintain all resources and schedule the functions in containers. Serverless computing thus enables developers to focus on their core business logic and leave server management and scaling to cloud providers. Unfortunately, existing serverless computing systems suffer from a key limitation that deprives them of enjoying significant speedups. Specifically, they treat each cloud function as a black box and are blind to which data the function reads or writes, therefore missing potentially huge optimization opportunities, such as caching data and colocating functions. We present Lambdata, a novel serverless computing system that enables developers to declare a cloud function's data intents, including both data read and data written. Once data intents are made explicit, Lambdata performs a variety of optimizations to improve speed, including caching data locally and scheduling functions based on code and data locality. Our evaluation of Lambdata shows that it achieves an average speedup of 1.51x on the turnaround time of practical workloads and reduces monetary cost by 16.5%.
- Published
- 2020
46. Simultaneous Multi Voltage Aware Timing Analysis Methodology for SOC using Machine Learning
- Author
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Vishant Gotra and Srinivasa Kodanda Rama Reddy
- Subjects
Computer science ,business.industry ,Signoff ,Static timing analysis ,Hardware_PERFORMANCEANDRELIABILITY ,Machine learning ,computer.software_genre ,Chip ,Turnaround time ,Power (physics) ,Hardware_INTEGRATEDCIRCUITS ,System on a chip ,Artificial intelligence ,business ,computer ,Power domains ,Voltage - Abstract
To improve gross margins, the semiconductor industry is focused on the PPA (power, performance, area) matrix of the SOC. The current trend is to put more IPs on the chips to enable multiple functionalities to support various applications. To optimize PPA of such SOCs, multi voltage and multi power domain design techniques are used due to which the timing signoff of the chip has to be done on multiple corners and multiple modes (MCMM). Single voltage timing analysis is easier. With the multi-level supply voltage and dynamic scaling features, the timing analysis complexity increases because timing signoff has to be done on different voltages and cross-voltage paths. Multi-voltage designs need exhaustive analysis of cross voltage domain paths to make sure all worst-case paths are identified under all voltage combinations. With numerous operating PVT corners, timing analysis across corners is very challenging. Simultaneous multi-voltage aware analysis (SMVA) do the analysis of all cross-domain paths under all voltage scenarios in a single run, without the need for margining that can add pessimism. In this paper, we propose a machine learning model, based on bigrams of path stages, to predict the timing slack divergence and cell delays across voltages. We identified the circuit parameters which affects the cell delays due to voltage changes and thereby causing the differences in the endpoint arrival times. We use the timing analysis data of a given testcase at multiple voltages and with the use of Classification and regression tree (CART) approach we develop a predictive model for the new arrival times due to the change in voltages. Experimental results show that our model is able to predict the timing path slack divergence with ~97% accuracy at different voltages on both clock and data paths with a lower turnaround time including the cross-voltage timing paths.
- Published
- 2020
47. Performance Optimization of Semi-Custom Memory in 7nm FPGA
- Author
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Mohammad Anees, Santosh Yachareni, Sourabh Aditya Swarnkar, and Kumar Rahul
- Subjects
First pass ,Criticality ,Gate array ,business.industry ,Computer science ,Feature (computer vision) ,Embedded system ,Hybrid approach ,business ,Field-programmable gate array ,Turnaround time ,Field (computer science) - Abstract
Designing memories which embeds multiple features involves greater challenges. Implementing additional functions to memory degrades memory performance. Applications demanding more features along with high-performance create design challenges for memories. Designing feature rich memories using complete custom approach increases design turnaround time. Generally, memory implementation in Field Programable Gate Array (FPGA) follow hybrid approach of custom and digital design techniques. Defining optimal clock-distribution network in such feature rich designs is one of the most important aspect of high-speed Silicon-on-chip (SoC) design. This paper demonstrates the custom approach by prioritizing various features in terms of criticality of timing requirements and significantly improve the clock tree performance. This approach opens new possibility for designing feature rich memory with high chances of first pass design on silicon. These kinds of memories can be seen in the FPGA’s, CPU’s, GPU’s.
- Published
- 2020
48. Towards Optimal System Deployment for Edge Computing: A Preliminary Study
- Author
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Dawei Li, Chigozie Asikaburu, Boxiang Dong, Sadoon Azizi, and Huan Zhou
- Subjects
020203 distributed computing ,System deployment ,Computer science ,Distributed computing ,020206 networking & telecommunications ,02 engineering and technology ,Turnaround time ,Base station ,Software deployment ,CloudSim ,0202 electrical engineering, electronic engineering, information engineering ,Enhanced Data Rates for GSM Evolution ,Mobile device ,Edge computing - Abstract
In this preliminary study, we consider the server allocation problem for edge computing system deployment. Our goal is to minimize the average turnaround time of application requests/tasks, generated by all mobile devices/users in a geographical region. We consider two approaches for edge cloud deployment: the flat deployment, where all edge clouds co-locate with the base stations, and the hierarchical deployment, where edge clouds can also co-locate with other system components besides the base stations. In the flat deployment, we demonstrate that the allocation of edge cloud servers should be balanced across all the base stations, if the application request arrival rates at the base stations are equal to each other. We also show that the hierarchical deployment approach has great potentials in minimizing the system's average turnaround time. We conduct various simulation studies using the CloudSim Plus platform to verify our theoretical results. The collective findings trough theoretical analysis and simulation results will provide useful guidance in practical edge computing system deployment.
- Published
- 2020
49. Modeling Architectural Support for Tightly-Coupled Accelerators
- Author
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David J. Schlais, Heng Zhuo, and Mikko H. Lipasti
- Subjects
010302 applied physics ,Out-of-order execution ,Computer science ,Distributed computing ,Concurrency ,Computation ,Speculative execution ,Memory bandwidth ,Context (language use) ,02 engineering and technology ,01 natural sciences ,Turnaround time ,020202 computer hardware & architecture ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Hardware acceleration - Abstract
As proposed accelerators target finer-grained chunks of computation and data movement, it becomes increasingly important to couple them tightly with the processor, avoiding long invocation delays. However, the large implementation design space of these Tightly-Coupled Accelerators (TCAs) makes it difficult to balance trade-offs between hardware complexity and accelerator performance. Previous performance models for accelerators focused on the penalties associated with loosely-coupled accelerators, which abstracted away many of the fine-grained interactions with complex out-of-order structures and program behaviors that have large impacts on TCA performance. In this paper, we introduce an analytical model that studies TCA behavior when interacting with the core, in the context of both high and low memory bandwidth applications supporting various levels of speculative and out of order (OoO) execution. Our analytical model reduces the turnaround time in early design stages when estimating performance gains over detailed simulation with tolerable error. We also discuss potential design choices that can impede the benefits that come with TCAs, and illuminate differences with traditional accelerators.
- Published
- 2020
50. Reducing the turnaround time of laboratory samples by using Lean Six Sigma methodology in a tertiary-care hospital in India
- Author
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G Varaprasad, Alok Kumar Samanta, and K Lokesh
- Subjects
Quality management ,Patient satisfaction ,Computer science ,DMAIC ,Six Sigma ,Operational efficiency ,Operations management ,Lean Six Sigma ,Turnaround time ,Value stream mapping - Abstract
Lean Six Sigma (LSS) is a Quality Improvement (QI) method that integrates the speed of lean principles and robustness of Six Sigma (SS). LSS methodology, though invented and employed in manufacturing sectors initially, is also accepted widely across service sectors. The objective of this work is to reduce the Turnaround Time (TAT) of the laboratory tests in the pediatric emergency department of a tertiary-care hospital in India. The applicability of LSS DMAIC (Define-Measure-Analyze-Improve-Control) methodology to reduce the TAT is explored. During the pre-intervention period, a total of 44 samples were sent to the lab for testing, and the average TAT was found to be 69 minutes. A multidisciplinary team of experts constructed the Value Stream Map (VSM), and each step in the process was analyzed. Through brainstorming and 5-why analysis, the root causes of delay were identified, and the corresponding improvement actions were finalized. During the course of the work, various lean wastes in the process were also identified and eliminated. A new process map was designed, and the improvised process was simulated using the simulation software ARENA and results were obtained. The results of the improvised process show a substantial reduction in TAT. The reduced TAT will decrease the overcrowding of patients and thus will result in smooth patient flow. Hence, through the systematic LSS approach, the opportunities for improvements can be identified and eliminated for better operational efficiency and patient satisfaction in the healthcare sector.
- Published
- 2020
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