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4 results on '"sampling rate reduction"'

1. A Manifold Regularization Approach for Low Sampling Rate Digital Predistortion With Band-Limited Feedback.

Author

Jiang, Chengye, Qiao, Wen, Yang, Guichen, Su, Lei, Han, Renlong, Tan, Jingchao, and Liu, Falin

Subjects
*BROADBAND communication systems, *PSYCHOLOGICAL feedback, *POWER amplifiers, *ELECTRICITY pricing
Abstract

Digital predistortion (DPD) is an effective linearization technique for RF power amplifiers (PAs), but conventional full sampling (FS) DPD systems use ADCs with three to five times signal bandwidth, and high-speed ADCs are expensive and power-hungry. In this article, we develop a novel band-limited DPD for reducing feedback sampling rate and acquisition bandwidth based on a general framework for semisupervised learning called manifold regularization (MR), which utilizes the geometry of unlabeled data to construct regularization terms for mitigating the overfitting problem. Considering the properties of DPD, we design a basis MR term and introduce it into the classical MR to obtain the extended MR (ExMR) method. To validate the proposed ExMR DPD method, experiments were conducted on two different RF PAs operating at 2.4 and 39 GHz, respectively. The test results demonstrate that the proposed ExMR DPD can linearize the RF PA with a 40-MHz acquisition bandwidth at 100-MHz input. The proposed method significantly reduces the cost and power consumption of the DPD system in comparison with the conventional FS DPD method, which provides a promising solution for broadband communication systems. [ABSTRACT FROM AUTHOR]

Published
2022
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2. Low-power adaptive pseudo noise code acquisition for spread-spectrum systems.

Author

Mau-Lin Wu and Kuei-Ann Wen

Abstract

A novel pseudo noise code acquisition combined with the newly proposed adaptive sampling rate and threshold control (ASTC) algorithm is derived for low-power spread-spectrum systems with complementary metal-oxide-semiconductor implementations. Low-power performance can be achieved by reducing the sampling rate of the proposed system while maintaining the system performance. The sampling rate is dynamically updated due to the change of the channel noise level. Under the assumptions that the channel is additive white Gaussian noise slow-fading channel, up to 74.3% reduction in power consumption compared to the conventional fixed-sampling rate and fixed-threshold architecture is demonstrated with insignificant increase of system complexity. The proposed architecture can be applied to the design of low-power and controllable-performance spread-spectrum communication systems. [ABSTRACT FROM PUBLISHER]

Published
2002
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3. A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

Author

Feng Wei Kuo, Chewn-Pu Jou, Lan-Chou Cho, Fu-Lung Hsueh, Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski, and Huan-Neng Ron Chen

Subjects
Engineering, oscillators, supply voltage reduction, Internet of Things, 1/f noise reduction, low-voltage oscillator, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 7. Clean energy, Radio transmitters, law.invention, Bluetooth, class-E/F 2 power amplifier, MOSFET circuits, law, Radio frequency, 0202 electrical engineering, electronic engineering, information engineering, Inductors, sampling rate reduction, direct DCO data modulation, class-E-F2 switching power amplifier, RF power amplifier, Transmitter, Electrical engineering, Q-factor, CMOS digital integrated circuits, all-digital PLL, Switching current-source oscillator, digital phase locked loops, Low-voltage oscillator, CMOS, constant current sources, ultra-low power radios, switching current sources, All-digital PLL, efficiency 36 percent, fully integrated Bluetooth low-energy transmitter architecture, metal density, power 5.5 mW, CMOS transistors, low-power transmitter, Low-power transmitter, energy-hungry RF circuits, Hardware_GENERAL, Electronic engineering, Hardware_INTEGRATEDCIRCUITS, Digitally controlled oscillator, Electrical and Electronic Engineering, power 3.6 mW, threshold voltage, switching current-source oscillator, business.industry, Amplifier, radiofrequency power amplifiers, 020208 electrical & electronic engineering, size 28 nm, 020206 networking & telecommunications, CMOS integrated circuits, radiofrequency integrated circuits, Internet of Things (IoT), Phase-locked loop, Bluetooth Low-Energy, low-power electronics, Bluetooth low-energy mode, business, digitally controlled oscillator, Low voltage, Switches
Abstract

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode. European Research Council

Published
2016

4. A 2.4 μm CMOS switched-capacitor video decimator with sampling rate reduction from 40.5 MHz to 13.5 MHz.

Author

Martins, R.P. and Franca, J.E.

Abstract

A description is given of the design and integrated-circuit implementation of a fifth-order elliptic lowpass switched-capacitor (SC) video decimator with a cutoff frequency of 3.6 MHz and sampling rate reduction from 40.5 MHz to 13.5 MHz. A recently proposed decimator architecture used to make the settling time requirements of the operational amplifiers similar to those of a conventional SC filter with switching frequency of only 13.5 MHz. The circuit is implemented using a 2.4-μm CMOS double-poly process yielding a total area of less than 1 mm2. The power consumption is less than 50 mW with a 10-V power supply [ABSTRACT FROM PUBLISHER]

Published
1989
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