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This paper discusses the sensitivity of programmable logic controllers (PLCs) to voltage sags based on mechanistic analysis and numerous tests. First, the sag sensitivity caused by different values of rated working voltage is shown through an analysis of the power supply and discrete input/output modules of PLCs. Second, a detailed sag-tolerance experimental scheme is proposed, and PLC sensitivity curves that differ from early curves are established through several experimental tests. Experiments are conducted with nine typical PLCs. The sensitivity of the power supply and discrete input modules are researched first, and then, the effect of the key characteristics of voltage sag, namely, magnitude, duration, points-on-wave of sag initiation, odd harmonics, multiple sags, and continuous sags, is tested. The uncertain area of the PLC sag tolerance is identified after intensively processing the extensive experimental data and curve fitting. A more accurate sag influence assessment for PLCs can be made with the given curves compared to the early curves. Furthermore, experiments have revealed that certain PLCs may work in an uncertain status during voltage sags. The reason and the method of elimination with the proper choice of dc bus capacitance for PLCs are also analyzed. [ABSTRACT FROM AUTHOR]

Programmable logic controllers (PLCs) are hard real-time embedded systems designed to interact with (through sensors and actuators) and control physical processes in pharmaceutical, manufacturing, energy, and automotive industries. PLCs are the fundamental building blocks in modern industrial automation systems; they are designed to operate in extreme, harsh environments for decades without interruption. This letter presents and evaluates a novel, scalable hardware/software architecture for multi/many-core PLCs capable of pipelining the “sensing-executing-actuating” stages of a control system and thus reducing the scan cycle time (SCT) and maintaining a high-throughput communication (HTC). SCT and HTC are two of the most important key performance indicators (KPIs) in industrial control systems because they determine the accuracy of the control algorithms. [ABSTRACT FROM PUBLISHER]

Large input voltage range and wide output current range are usually needed for dc-dc converters. For these input and output conditions, the converter's efficiency can be maximized by a proposed method, efficiency-optimized switching-frequency (EOF) control. The optimal switching frequency for maximizing the efficiency is generated by the low-complexity and low-power EOF generator. A reconfigurable compensator is developed for improving the load regulation and the transient response. A piecewise-linear current sensor (PLCS) is employed to reduce controller power loss without sacrificing the sensing accuracy. With the aforementioned three proposed methods, a monolithic current-mode dc-dc buck converter is implemented in a 0.35-μm 3.3-V CMOS process. The measured power-loss reductions and efficiency improvements achieve 16 and 15 mW, and 16% and 1%, both in light and heavy loads, respectively. The load regulation and the transient recovery time are improved by 40 mV and 12 μs, respectively, while the PLCS can reduce 3 mW of power loss. Compared with other published converters in 0.35-μm CMOS process, the implemented converter achieves a higher efficiency of 96.3% and smaller chip area of 0.97 mm. [ABSTRACT FROM AUTHOR]