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A thorough investigation of major contributors to out-of-band emission (OOBE) in transmitters (TXs) utilizing digital modulation schemes is provided. Specifically, the paper delves into the detrimental effects of phase noise of the local oscillator (LO), typically realized using a phase-locked loop (PLL), on the OOBE phenomenon. Furthermore, the effects of the circuit nonlinearity in a TX, widely recognized as a primary contributor to spectral regrowth and elevated levels of OOBE, are investigated. Additionally, the impact of filtering and bandwidth (BW) limitation on OOBE is taken into account. Comprehensive simulations verify the accuracy of the analytical study. The results provided throughout this paper can be used to determine the linearity and phase noise requirements of different blocks, such as PLL and power amplifier (PA) within a TX chain to design a system complying with a specific mask emission dictated by a particular standard.

The dynamic coupling effect, which is introduced by the dual-sequence phase-locked loops (PLLs) used in doublyfed induction generator (DFIG) based wind energy generation systems (WEGSs) during asymmetric low voltage ride-through (LVRT) in weak grid, needs attention. In order to study this new dynamic coupling effect, an equivalent two-degree-of-freedom (2-DOF) spring damper particle model is used in this paper to develop a small-signal model for the dual-sequence PLLs. The dynamic interaction between the positive-sequence (PS) and negative-sequence (NS) PLLs is unveiled. Moreover, the impact of the dynamic coupling between the dual-sequence PLLs on the dynamic stability during the steady-state stage of an asymmetric fault is analyzed. The analysis results show that the dynamic coupling between the dual-sequence PLLs will cause drift in the frequency and damping for the PS and NS PLL modes. This will change the instability modal of the system and introduce the risk of dynamic instability. Hence, the effectiveness of existing control strategies for enhancing the dynamic stability will be decreased. Finally, a novel PLL structure is designed to improve the dynamic stability of the system during the steady-state stage of an asymmetric fault. The effectiveness of the proposed strategy is verified by simulations and experiments.

This article presents an enhanced power-synchronized grid-following inverter (ePSGFLI) for reliable and stable integration of renewable energy resources into the grid. By eliminating the use of a phase-locked loop (PLL) in the control loop, the ePSGFLI resolves instability issues commonly associated with conventional PLL-based grid-following inverters (GFLIs). Furthermore, in contrast to existing PLL-less strategies like linear parameter-varying control of power-synchronized GFLI (LPV-PSGFLI), which suffer from steady-state errors and instability during grid frequency deviations, the proposed ePSGFLI ensures stable performance without steady-state errors, regardless of the strength of the grid. To achieve robust and accurate tracking of grid frequency, even under significant deviations, while effectively decoupling the active and reactive power loops, the ePSGFLI employs a loop-shaping design procedure for real-time auto-tuning of the multivariable second-order 2-by-2 outer power controller. The effectiveness of the proposed ePSGFLI is validated via simulations in MATLAB/Simulink and experimental testing under both strong and weak grid connections. The results demonstrate its superior performance compared to existing PLL-based and PLL-less control strategies in terms of stable operation and accurate tracking of power and grid frequency.

Voltage source converter based high-voltage direct current (VSC-HVDC) transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources. However, connecting a voltage source converter (VSC) to an AC weak grid may cause the converter system to become unstable. In this paper, a phase-shift phase-locked loop (PS-PLL) is proposed wherein a back electromotive force (BEMF) observer is added to the conventional phase-locked loop (PLL). The BEMF observer is used to observe the voltage of the infinite grid in the stationary $\alpha\beta$ frame, which avoids the problem of inaccurate observations of the grid voltage in the $dq$ frame that are caused by the output phase angle errors of the PLL. The VSC using the PS-PLL can operate as if it is facing a strong grid, thus enhancing the stability of the VSC-HVDC system. The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL, which makes it easy to implement. In addition, because it is difficult to obtain the exact impedance of the grid, the influence of short-circuit ratio (SCR) estimation errors on the performance of the PS-PLL is also studied. The effectiveness of the proposed PS-PLL is verified by the small-signal stability analysis and time-domain simulation.

This paper offers a detailed analysis as well as a tuning and discretization approach of the presented frequency-fixed dual second order generalized integrator based phase-locked loop (FFDSOGI-PLL) for three-phase power systems. The method combines different single- and three-phase PLL approaches by ensuring high phase- and frequency tracking properties. The comparison with the standard frequency-variable DSOGI-PLL and three different recently published three-phase frequency and phase-angle estimation systems shows, that this approach gives a fast and stable phase and frequency detection of the grid voltage with very low computational burden. The results are applicable to, for instance, photovoltaic or frequency converters or active power filters.

In this article, we aim to design a simple dc immune phase-locked loop (PLL) for single-phase applications. The dc offset is inherently rejected using only two delay operators. The dc offset in the synchronization unit is a challenging problem that causes oscillation in the estimated grid information. Using conventional filters to solve this problem is ineffective since this degrades the synchronization unit's dynamic performance. Different PLLs have been introduced in this article to mitigate the dc offset. Each has its merits and demerits, such as complex structure, high computational burden, and slow transient response. The proposed PLL incorporates two cascaded delayed signal cancellation operators with an arbitrary-length time delay, rejects the dc offset, and perfectly synchronizes with the grid. This article also presents a small-signal model to facilitate the loop filter design and stability analysis. Besides the simulations, the PLL's performance is validated experimentally under various disturbance conditions, with comparisons with other PLLs. [ABSTRACT FROM AUTHOR]

This article proposes a novel sensorless control strategy for permanent magnet synchronous motor drives using reduced order quasi resonant-based extended state observer (ROQR-ESO) and Newton–Raphson method-based phase-locked loop (NRM-PLL). Due to the low-pass filtering characteristics, the conventional linear extended state observer (LESO) is not adequately able to track the fast-varying back electromotive forces (BEMFs). On this basis, the ROQR-ESO, which plants a ROQR controller into the internal model of conventional LESO, is presented to obtain BEMFs without phase lag. Moreover, the NRM-PLL, regarded as an improved finite position set-PLL, is proposed. After the rotor position is divided into four parts by utilizing a position quartering method, the extremely accurate rotor position can be obtained only by three iterations. In this method, no parameters need to be adjusted and great dynamic response can be achieved. The capacity of the proposed scheme is verified on a 750 W permanent magnet synchronous motor drive platform. [ABSTRACT FROM AUTHOR]

The voltage source converters (VSCs) are used to interface and control the renewable energy resources that are integrated into the power grids. However, a weak grid connection raises a stability problem for grid synchronization of the grid-feeding current-controlled VSCs (CCVSCs). This paper handles modeling and controller design for stabilizing the weak grid connection of CCVSCs. The impedance modeling/shaping of the VSC has been recognized as an effective tool to analyze and design the dynamics of the VSC. But an explicit and accurate impedance model of the CCVSC is required. Particularly, modeling the impact of the phase-locked loop (PLL) synchronization unit on the impedance model of the CCVSC is complex. Therefore, at first, an efficient impedance model of the CCVSC is developed while the impact of the PLL is rigorously considered through a complex procedure that results in an explicit/accurate impedance model. The developed impedance model is used to conduct passivity/weak grid connection stability analysis to clarify the underlying causes of instability problems. Then, a novel PLL, with an in-loop low-pass filter (LPF) to account for harmonics/asymmetries, is proposed with enhanced characteristics using the state feedback control. The impedance shaping method (with the aid of the impedance model) is utilized to design the state feedback gains. The state feedback loops provide degrees of freedom for bandwidth design of the PLL considering the current/power control loops and stabilize the system under weak grid connection/distorted conditions. Simulation results prove the accuracy and effectiveness of the models.

Resolvers are widely used as position sensors to obtain angle information. The resolver requires the excitation signal and its amplitude is modulated by the rotor position. The envelope of the modulated signal can be detected precisely only when the samplings are synchronized with the excitation signal. A large error can occur if the synchronization fails. In this paper, the resolver signals are sampled in synchronization with the pulsewidth modulation (PWM) carrier, not the excitation signal. When the resolver excitation signal frequency and the PWM carrier frequency are different, the envelope cannot be detected, so additional signal processing is required to obtain the angle information. For signal processing, multiple auxiliary signals are synthesized based on the sampled signals and quadrature demodulation is performed. A detailed error analysis according to the PWM frequency and motor speed is also performed. The effectiveness is demonstrated through simulation and experimental evidence.

MEMS resonant accelerometers are robust to electromagnetic interference and have higher sensitivity and resolution. However, they are susceptible to temperature variation, which may limit this type of sensor used in high-end applications. This paper proposes a TDS-PLL with MEMS VCO for MEMS resonant accelerometers to be immune to temperature drift. The theoretical analysis of TDS-PLL MRA demonstrates it can suppress the temperature drift, which is verified by simulation and measurement results. Measurement results of the TDS-PLL MRA show that the bias instability is $13.15~\mu \text{g}$ and the noise level is $7.04~\mu \text{g}/\surd $ Hz with 0.32g full scale at room temperature. The temperature coefficient of bias stability in TDS-PLL MRA achieves 2.21 mg/°C in a temperature range of 300K to 360K, which is lower 5.5 times than that of the traditional PLL MRA with frequency shift. [2022-0098] [ABSTRACT FROM AUTHOR]

Phase–locked loop (PLL) is commonly used for the grid-connected voltage-source converter (VSC) to synchronize with the grid. Under weak grid conditions, it has been found that the frequency-dependent characteristic of the network impedance inherently introduces a positive feedback loop into PLL. Previous studies focused on the PLL analysis intuitively believe that the positive feedback loop will deteriorate the dynamic performance of the PLL. However, this conclusion is not rigorous since only the dynamic of the PLL is considered and the theoretical analysis is insufficiency to reveal the influence of the positive feedback loop on system stability. In this paper, the impact of the frequency-dependent network on VSC stability is quantified in terms of the overall system based on the damping torque analysis. It is found that the influence of the positive feedback loop on stability depends on the parameters of the PLL and the damping of the dominant eigenvalues. Besides, an angular frequency feedback scheme is proposed to eliminate the adverse effect of the frequency-dependent network and enhance the stability of the VSC under weak grid conditions. Time-domain numerical simulations and reduced-scale experiments are performed to validate the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

Accurate rotor position is significant for the back electromotive force (EMF)-based sensorless interior permanent-magnet synchronous motor (IPMSM) control. However, the ±(6 h±1)th harmonics will appear obviously in the estimated back-EMF due to the effect of the inverter nonlinearity and flux spatial harmonics. These harmonics will subsequently result in the ±(6 h)th harmonic pulsation in the estimated rotor position. In order to deal with this issue, a new complex-coefficient synchronous frequency filter (CCSFF)-based sliding mode observer combined with a quadrature phase-locked loop (PLL) is proposed to mitigate the back-EMF voltage distortion. Therefore, the performance of the position estimation is remarkably improved. The proposed CCSFF possesses both bandpass-filtering and frequency-adaptability characteristics. It can pass the fundamental component without magnitude attenuation and phase delay in different frequency scenarios. Moreover, the linearized model of the proposed CCSFF-PLL-based position estimation system is established and a systematic parameter design is presented to obtain promising dynamic performance. The effectiveness and feasibility of the proposed method are confirmed by experiments on a 1.5-kW IPMSM test platform. [ABSTRACT FROM AUTHOR]

This work presents a fully integrated 140-GHz transmitter (TX) achieving a data rate of 160 Gb/s with ~1-pJ/b efficiency in the 22-nm Intel FinFET technology. The TX leverages a wideband radio frequency digital to analog converter (RF-DAC) architecture with embedded 4:1 multiplexer, and it is integrated with a sub-sampling quadrature phase-locked loop (PLL), frequency tripler, local oscillator (LO) buffers, wideband two-stage power amplifier (PA), and on-chip SRAM/pseudorandom binary sequence (PRBS) for high-speed data generation. The TX achieves 120/160-Gb/s 16 quadratic-amplitude modulation (QAM) with −19/−17-dB error vector magnitude (EVM) at an output power of +1.5/+0.8 dBm. [ABSTRACT FROM AUTHOR]

Power electronic converters for integrating renewable energy resources into power systems can be divided into grid-forming and grid-following inverters. They possess certain similarities, but several important differences, which means that the relationship between them is quite subtle and sometimes obscure. In this article, a new perspective based on duality is proposed to create new insights. It successfully unifies the grid interfacing and synchronization characteristics of the two inverter types in a symmetric, elegant, and technology-neutral form. Analysis shows that the grid-forming and grid-following inverters are duals of each other in several ways including a) synchronization controllers: frequency droop control and phase-locked loop (PLL); b) grid-interfacing characteristics: current-following voltage-forming and voltage-following current-forming; c) swing characteristics: current-angle swing and voltage-angle swing; d) inner-loop controllers: output impedance shaping and output admittance shaping; and e) grid strength compatibility: strong-grid instability and weak-grid instability. The swing equations are also derived in dual form, which reveal the dynamic interaction between the grid strength, the synchronization controllers, and the inner-loop controllers. Insights are generated into cases of poor stability in both small-signal and transient/large-signal. The theoretical analysis and simulation results are used to illustrate cases for single-inverter systems, two-inverter systems, and multi-inverter networks. [ABSTRACT FROM AUTHOR]

Changes in the orthogonal signal generator (OSG) configuration of the standard second-order generalized integrator-based phase-locked loop (S-SOGI PLL) have shown to offer an improved low-voltage ride-through capability. However, the resulting PLLs: highpass SOGI (H-SOGI) and lowpass SOGI (L-SOGI) PLLs have no dc-offset estimation capability and lack robustness to disturbances. Therefore, this article focuses on maximizing the merits of H-SOGI and L-SOGI PLLs for grid and industrial applications by incorporating dc-offset estimation and enhancing their disturbance rejection capability. Accordingly, two varieties of SOGI PLLs, namely: extended state highpass SOGI (ES-H-SOGI) and extended state lowpass SOGI (ES-L-SOGI) PLLs are proposed. In the proposed PLLs, states of the OSGs are extended to achieve dc-offset estimation and rejection, while frequency-adaptive implementation of the moving average filter (MAF) is developed to achieve complete harmonic rejection at off-nominal frequencies of the input voltage. To alleviate the undesirable effect of the MAF in terms of the PLL's slow transient response, frequency-adaptive implementation of a phase-lead compensator is introduced. In this article, design guideline that achieves an optimal tradeoff between disturbance rejection and dynamic performance in the ES-H-SOGI and ES-L-SOGI PLLs is presented. Finally, experimental comparison between the proposed ES-H-SOGI and ES-L-SOGI PLLs and their ES-S-SOGI PLL counterpart is carried to show that the proposed PLLs outperform the ES-S-SOGI PLL in terms of dynamic performance while achieving enhanced disturbance rejection capability. [ABSTRACT FROM AUTHOR]

For the grid-connected inverter, grid voltage sag can be a typical phenomenon. From the prospective of safe and robust operation, the inverter should be stable when the grid voltage sag (or large disturbance) occurs. Although the inverter stability in this case has attracted considerable attentions, few studies have given suggestions on the system stability boundary and parameter design. To fill this gap, this article deeply discusses the large-signal stability of the system under different situations and reveals the quantified impact of the phase-locked loop (PLL) on the large-signal stability of the system based on the fundamental current-source model. The large-signal stability criterion and boundaries for grid voltage sags are established, which are instructive to the design of PLL parameters. Besides, a novel design guideline for the PLL parameters is proposed to ensure the robust operation of the system both under the steady-state and grid voltage sags, as well as to achieve good dynamic performance after large disturbance occurs. The theoretical, simulation, and experimental results show that the proposed stability boundary has certain accuracy and the PLL parameters design guideline can ensure the system stability both under steady-state and grid voltage sag conditions. [ABSTRACT FROM AUTHOR]

In this article, we studied the parameters identification problem for the single sinusoidal signal based on the finite-time observer technique. After representing the sinusoidal signal with known frequency as a second-order time-invariant system, a finite-time observer-based estimation strategy is designed based on the homogeneous system theory to obtain unknown amplitude and phase angle. When the signal frequency is unknown, the original signal will be constructed into a third-order nonlinear system, which is challenging to design the corresponding state estimator. Based on the Lyapunov analysis method and adding a power integrator technique, a finite-time estimation scheme is developed and analyzed strictly. Finally, for a single-phase grid signal, some experimental results are provided to illustrate the efficacy of the proposed method. [ABSTRACT FROM AUTHOR]

This article proposes a new control strategy in stationary frame to improve the operational robustness of voltage source converters (VSCs) under weak grid conditions. First, dynamics of the phase-locked loop (PLL) are incorporated into the model of a grid-connected VSC in stationary reference frame. It is rigorously shown that the three-phase PLL introduces cross-coupling terms between the two control channels. Second, based on the augmented model, a multivariable controller is proposed which combines the current control feedback gains with PLL feedback gains. Third, the gains of the controller are designed using an optimal control theory approach. It is shown through theoretical analysis, computer simulations, and a laboratory experimental setup that the proposed controller improves the stability margins of the VSC during weak grid conditions. More specifically, under a given identical operating conditions, while the conventional controller’s responses become increasingly oscillatory for short-circuit ratio (SCR) below 1.95 and eventually becomes unstable at SCR=1.26, the proposed controller exhibits smooth and stable responses for SCR as low as 1. The proposed controller also produces cleaner sinusoidal currents during unbalanced grid voltages. [ABSTRACT FROM AUTHOR]

Renewable energy sources (RESs) are highly penetrated in power systems through phase-locked loop (PLL) synchronized converters. Under severe grid voltage sags, PLL-synchronized RES system is susceptive to transient instability and tripping from the grid due to inappropriate current injection. The existing literatures mainly focus on synchronization instability issues of a single grid-connected RES system, and the effect of the interaction between them is rarely studied. To fill this gap, this paper aims to clarify the interaction mechanism and characterize stability boundary of paralleled PLL-synchronized RES system with different converter parameters. More specifically, the effect of current injection angle and magnitude on transient synchronization stability is investigated for guiding current injection reference design during low voltage ride-through (LVRT) and rated capacity option of RESs. First, the transient interaction model of the paralleled converter system is developed, and interaction mechanism under different current injection angles is revealed. Next, stability region analysis is performed to evaluate the impact of current injection magnitude, wherein current injection boundary is obtained. Then, a current injection design method is proposed for improving both transient stability and voltage support. The theoretical analysis and the proposed method are validated by simulation results. [ABSTRACT FROM AUTHOR]

An accurate and prompt estimation of phase angles, frequency, and magnitudes of the grid voltage is extremely important in paving a good platform for a fast and reliable operation of power grid monitoring, protection, and control. The phase-locked loop (PLL) served this purpose for decades, while the concept of the frequency-locked loop (FLL) has been proposed more recently. Even though the FLL and the PLL share some similarities, some differences still exist. Further research on FLLs can boost their capabilities and open up new windows in designing devices for grid synchronization. Multiple delayed signal cancellation (MDSC) filters are a peculiar system of filters. Their applications to FLLs can enrich FLL’s performance. This article focuses on applying the stationary reference frame MDSC filters at in-loop and prefiltering stages of the FLL and compares its effectiveness with widely used cascaded delayed signal cancellation (CDSC) and complex bandpass filter (CBF) based filtering techniques. The application of the $K$ -factor-methodology-based controller design to FLLs has also been explored for dynamic performance enhancements. A new cascaded multiple delayed signal cancellation (CMDSC) filter is proposed and is compared with its CDSC counterpart proposed in the literature to address the effects of dc offsets and imbalances under adverse grid conditions. The effectiveness of the proposed method is verified through OPAL-RT real-time simulations and dSPACE ds1104 and TMS320F28335 microcontroller experimental test bench. [ABSTRACT FROM AUTHOR]

The instability issue of the grid-connected Voltage Source Converter (VSC) dominated by phase-lock loop (PLL) is investigated using the electrical torque method in this paper. The system dynamic model and steady-state relationship of variables are first established. Then, a basic two-order model representing the PLL natural oscillation mode is extracted. The impacts of the current control loop and altering current grid (ACG) on the PLL oscillation mode are derived using the electrical torque method. As a result, analytical expressions of the system synchronous and damping coefficients are obtained. Based on the derived synchronous and damping coefficient, qualitative evaluations of the impacts of the system parameters on the oscillation frequency and system stability can be achieved. It is drawn that a small PLL time constant, low infinite source voltage, heavy load, reactive power absorption, and long electrical distance will deteriorate system stability. Moreover, a sufficient analytical stability criterion for the grid-connected VSC is derived from the damping coefficient. The system stability can be directly evaluated through the operation points and system parameters, and the quantitative evaluation of the system stability is achieved. The eigenvalue analysis and electromagnetic transient simulation have verified the reliability and effectiveness of the theoretical analysis. [ABSTRACT FROM AUTHOR]

In single-phase voltage source inverters under a weak grid, the frequency coupling, caused by the asymmetrical system structure, poses a challenge to system modeling and controller design. In this article, a frequency coupling suppression control strategy is presented, where all the frequency coupling components in the current reference are eliminated. As a result, the single-phase grid-tied inverter is directly modeled as a simple single-input single-output (SISO) admittance rather than a complicated multiple-input multiple-output admittance matrix. The SISO admittance model is simple, compact, and accurate, which facilitates design-oriented analysis. The admittance characteristic analysis shows that the Symmetrical phase-locked loop (Sym-PLL) has a critical impact on the system stability under weak grid conditions. To improve the system stability, a prefilter-based impedance-shaping control strategy is proposed by mitigating the negative resistor behavior of the Sym-PLL. Finally, simulations and experimental results validate the effectiveness of the frequency-coupling suppression control strategy. [ABSTRACT FROM AUTHOR]

This article presents a new current controller in the synchronous reference frame and its associated design for enhancing the performance of three-phase grid-connected inverters, especially against weak-grid conditions. The existing controllers do not perform strongly during high-impedance grid conditions and lead to oscillations and instability issues due to the interactions between the synchronization and control units. The proposed controller addresses this issue by 1) deriving a linear model of the three-phase phase-locked loop (PLL), 2) integrating the PLL model into the current controller design, 3) using a multivariable control design for multi-input multi-output systems, and 4) designing the controller gains using optimal linear quadratic theory. The proposed controller has superior performance over a substantially wider range of weak-grid conditions compared to conventional controllers. Extensive simulation and experimental results are presented in order to validate and reveal the desirable performance of the proposed controller. [ABSTRACT FROM AUTHOR]

This work presents an ultra-low jitter, direct $W$ -band phase-locked loop (PLL). Using the proposed power-gating injection-locked frequency multiplier (PG-ILFM)-based phase detector (PD) that can maintain a high phase-error-detection gain even at high frequencies above 100 GHz, this $W$ -band PLL can achieve a very low in-band phase noise. Due to this intrinsically low in-band phase noise, the bandwidth of the PLL can be extended so that it can suppress the poor phase noise of the $W$ -band voltage-controlled oscillator (VCO). The frequency-offset canceller (FOC) is also presented to remove the possible frequency offset between the main VCO of the PLL and the replica VCO of the PG-ILFM-based PD. Operating in the background, the FOC can ensure high phase-error-detection gain and wide loop bandwidth and, thus, the low-jitter performance of the PLL. The proposed PLL was fabricated in a 65-nm CMOS process, and it used a power of 22.5 mW and an area of 0.16 mm2. The rms jitter, integrated from 1 kHz to 300 MHz, was 82 fs at 102 GHz. It also achieved the FoMJIT of–248.2 dB, which is the best among the state-of-the-art $W$ -band frequency synthesizers. [ABSTRACT FROM AUTHOR]

This article presents approaches for efficient modeling and systematic design of enhanced phase-locked loop (ePLL) structures. While different ePLL structures have found a wide acceptance for various applications, their modeling and design aspects have not been fully and systematically reported in the existing literature. This article fills this gap by presenting an effective modeling approach for both the single- and three-phase ePLLs. The models are derived with a view to minimize the number of parameters to be adjusted to simplify the design. The models are then used to develop systematic design algorithms for their parameters. As an example, application of the ePLL in a grid-connected inverter is formulated and studied through simulation and experimental results. The design and simulation files are made available. [ABSTRACT FROM AUTHOR]

Considering that the traditional linearization method cannot accurately analyze the grid-tied inverter (GTI) system with nonlinear nature, in the single-phase case, a novel nonlinear model for the GTI system considering nonlinear factors, including synchronous reference frame phase-locked loop (PLL) and duty-cycle saturation in pulsewidth modulation, is proposed, and the corresponding global asymptotic stability condition is given. Specifically, some system nonlinear factors, e.g., duty-cycle saturation phenomenon and Park (dq) transformation and cosine operation in second-order generalized integrator-based PLL (SOGI-PLL), are investigated, and their sector-bounded conditions are derived. In order to seek less conservative results, the system state of the SOGI-PLL is restructured such that the linear part of the PLL system can be stabilized. Then, the nonlinear state-space model with sector bounded for the whole GTI system is formulated. Furthermore, the deduced sector conditions are introduced into the derivation of the Lyapunov function by using the S-procedure lemma, and the global asymptotic stability condition of the inverter system is, thus, obtained. The system stability regions under different grid impedances, current references, and control parameters are further analyzed. Finally, the effectiveness of the proposed theories is fully supported by transient experimental results. [ABSTRACT FROM AUTHOR]

Suppressing the negative effects of grid voltage harmonics on the estimated frequency of a phase-locked loop (PLL) is a challenge in literature. This article proposes an easy-to-implement quadrature signal generator (QSG) to attenuate the oscillations on the estimated frequency in single-phase grid-connected inverters, which use second-order generalized integrator (SOGI)-PLL. It is shown that SOGI exerts a stronger filtering effect in generating the quadrature signal than the in-phase signal. Against this background, in this work, a modified integrator is introduced into the path of the in-quadrature signal to generate another in-phase component with much lower harmonic content. The proposed method imposes only a small computational burden on the existing SOGI-PLL compared to the previously presented methods that address the input voltage harmonic problem. Moreover, this method can work properly within the allowable range of grid voltage frequency deviations. The proposed integrator benefits from an error-decaying mechanism to overcome dc drift in pure integrators. The integrator has been designed based on theoretical equations. The validity of the proposed QSG and theoretical equations is evaluated using simulations and experimental studies. A fixed-point representation of the proposed QSG is also provided for implementation on low-cost microcontrollers. [ABSTRACT FROM AUTHOR]

The wide bandwidth of phase-locked loop (PLL) will increase the negative real part of the output impedance of the grid-connected inverter (GCI), thus destroying the stability of the weak grids. This article proposes a novel method to improve the system stability through decoupling the PLL and grid impedance. Initially, the coupling relationship between PLL and grid impedance is revealed. It can explain why the choice of PLL bandwidth and the grid impedance magnitude is limited. Then, the decoupling method is proposed where the primary control structure of GCI does not need to change and uses the structured voltage, the product of PCC voltage and grid admittance, as the improved input of PLL. The proposed method can achieve the full-frequency passive of the output impedance of GCI even if the PLL has high bandwidth and the impedance measurement error is up to 60%, which means the adverse stability effect of PLL on the system is eliminated. The theoretical analysis is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

This article proposes a 3.2-GHz subsampling phase-locked loop (SSPLL)-based injection-locked clock multiplier (ILCM) using a subsampling delay-locked loop (SSDLL). The proposed ILCM achieves a superior noise reduction effect at low offset frequency because of the high feedback gain of SSPLL. Also, SSDLL is proposed for background phase calibration between SSPLL and injection. Since SSPLL and SSDLL use identical SSCP, the power consumption of the frequency and phase calibration is only 1.32 mW. This work is fabricated in a 65-nm CMOS process, and the 10-kHz phase noise is improved by 8.6 dB. The rms jitter from 10 kHz to 30 MHz is 178 fs. The chip-to-chip variations (20 chips) are 17 and 169 fs with/without SSDLL, respectively. The measured results show that FoM1, FoM2, and total power consumption are −245.1, −260.1 dB, and 9.85 mW, respectively. [ABSTRACT FROM AUTHOR]

This article focuses on the modeling and stability analysis of the typical single-phase phase-locked loop (PLL) based on second-order generalized integrator (SOGI). Traditionally, SOGI-based PLL (SOGI-PLL) is linearized as the linear time-invariant (LTI) model for the stability analysis and parameter design. Yet, the PLL has periodical nature due to the periodical variation of the grid voltage. The traditional LTI model for PLL thereby reduces the precision of stability analysis. For addressing this problem, an accurate linear time-periodic (LTP) model of the single-phase SOGI-PLL is proposed in this article. The proposed model can precisely characterize the coupling nature of phase, frequency, and amplitude estimated by SOGI-PLL. A precise stability region of SOGI-PLL, thereby, can be derived from the proposed LTP model. The effectiveness of the proposed LTP model for SOGI-PLL is verified by simulation and experimental tests. [ABSTRACT FROM AUTHOR]

In this article, we analyze the negative impact of phase-locked loop (PLL) on the stability of the doubly fed induction generators system. The small-signal disturbance of PLL mainly affects the coordinate transformation of the rotor current and introduces a negative resistance within PLL bandwidth. Two impedance reshaping methods are carried out to weaken this negative resistance. A virtual impedance in the conventional current control is added to the first reshaping method. The second reshaping method completely removes the coordinate transformation of the rotor current by switching the control target from current to power. The difference between these two reshaping methods is analyzed based on the equivalent single-input single-output impedance model. The experimental results validate the effectiveness of these two reshaping methods and the superiority of the second reshaping method at a lower short-circuit ratio. [ABSTRACT FROM AUTHOR]

The stability of the grid-connected inverter (GCI) system in weak grids is deteriorated due to the asymmetric positive-feedback loops (APFLs) introduced by the phase-locked loop (PLL) structure. Under the same main circuit parameters and control loop parameters, the small-signal models of the GCI controlled in dq domain and αβ domain are constructed, respectively. Compared with the small-signal model of the GCI controlled in dq domain, the number of APFLs introduced by the PLL of GCI controlled in αβ domain is one less. Moreover, the mechanism why the stability of the GCI controlled in αβ domain is stronger than that controlled in dq domain is analyzed. Meanwhile, the influence degree and mechanism of the APFLs in different paths of the small-signal models for the stability of GCI are revealed for the first time. This lays a theoretical foundation for the analysis and design of asymmetric control strategies used to improve the stability of GCI in weak grids. Finally, simulations and experiments verify the correctness of the theoretical analysis. [ABSTRACT FROM AUTHOR]

Based on a detailed analysis of harmonic generation in ring-based injection-locked frequency dividers (ILFDs), this article shows that concurrent injection signals can be generated in these stages by driving both tail and direct injectors with the same input signal. Based on this result, a novel ring-based divide-by-five ILFD is presented, where multi-injection is reinforced by a dual-path scheme, largely broadening the locking range with no penalty in power dissipation. The stage, implemented in a 28-nm CMOS process, operates over the 8-to-101.6-GHz frequency range achieving a >20% locking over the 13.6–69.1-GHz interval, with 5.6-mW maximum power consumption from a 0.9-V supply. The stage also achieves 101.6 GHz, the highest operating frequency among state-of-the-art CMOS ILFDs by five, with 2.6% locking range. [ABSTRACT FROM AUTHOR]

We present a low-power and low jitter two-stage 2.46–4.92-GHz clock multiplier using a 38.4-MHz reference clock. The proposed clock multiplier implements an $8\times $ clock multiplication with a delay-locked loop and an edge combiner (EC) in the first stage. The regulated supply of the voltage-controlled delay line and EC within the delay-locked loop limits the first-stage clock multiplication voltage sensitivity. An in-depth phase noise analysis of the first stage with the proposed phase domain modeling and spur analysis in the EC helps low-power clock multiplier design. The first-stage output injection locks a pseudo-differential ring oscillator embedded in a frequency tracking loop, thereby achieving a $64\times $ – $128\times $ clock multiplication in the second stage. In collaboration with the simulated phase noise from sources, a system-level phase noise modeling defines the design specifications of the two stages for minimum output jitter in a given power budget. Fabricated in a 65-nm CMOS process, the first-stage clock multiplier achieves an integrated jitter 761 fsrms at 307.2 MHz while consuming 2.5 mW. The mismatch and offset-induced systematic jitter is calibrated, giving −53.4-dBc reference spur at the first-stage output. The second-stage injection-locked clock multiplier adds low random jitter to the first stage with total output jitter 825 fsrms at 4.92 GHz, −28.2-dBc reference spur, and 3-mW power consumption. [ABSTRACT FROM AUTHOR]

This article presents a 23.9–29.4 GHz digital LC-phase-locked loop (PLL) architecture with a low phase noise (PN) and power-efficient coupled frequency doubler for 224 Gb/s PAM-4 transmitter clocking. The proposed frequency doubler is designed with two oscillators running at 14 and 28 GHz which are coupled by a transformer. Compared to a conventional frequency doubler or a two-way coupled oscillator, the coupling between the 14 and 28 GHz oscillators provides extra PN reduction as the 14 GHz oscillator can achieve lower PN than the 28 GHz one. In addition, by stacking the two oscillators through the transformer, the current is reused and hence power consumption is reduced. To optimize the PN performance across process, voltage, and temperature (PVT), a compact and power-efficient frequency-tracking loop (FTL) is implemented. The 14 GHz oscillator output is fed to the PLL feedback divider rather than the doubled output, which enables power saving in the prescaler divider in the feedback path. The proposed PLL is fabricated in 10 nm FinFET technology and the PLL achieves a 65 fs random jitter at the transmitter output after a 1st-order 4 MHz-BW CDR filtering which enables the industry’s first 224 Gb/s PAM-4 transmitter. Compared with a reference NMOS-GM LC-digitally controlled oscillator (DCO) implemented on the same die, the proposed coupled frequency doubler achieves 4.75 dB lower PN with only a 25% power consumption increase. The LC-PLL consumes 17.1 mW from a 0.8/1.0 V regulated supply and occupies an area of 0.088 mm2. [ABSTRACT FROM AUTHOR]

This study presents a design of a 94-GHz high-performance and highly compact frequency-modulated continuous-wave radar sensor. In this sensor, an $X$ -band CMOS-based all-digital phase-locked loop chip, $W$ -band SiGe-based transceiver monolithic microwave integrated circuit (MMIC), and $W$ -band GaN-based MMIC power amplifier (PA) are heterogeneously integrated (HI). Each part of the 130-nm bipolar complementary metal-oxide-semiconductor (BiCMOS) SiGe-based transceiver MMIC is designed to include a low-noise amplifier, PA, octupler, mixer, and lange coupler. The fabrication process of our in-house silicon-based MEMS photosensitive composite film is developed to provide very high-density integration and very low insertion loss of interconnections between chips. The HI front end of the radar sensor is measured on-wafer with a high output power of 22 dBm. Moreover, a low double-sideband noise figure (NF) of 10.2 dB is obtained. Bonding–substrate integrated waveguide (SIW)–WG transitions between the heterogeneously integrated front end and the antenna are specially designed and verified. A 2.3-dB degradation is observed, where 19.7 dBm is measured at the transmitter WG WR-10-flange. Thus, the sensor offers a 55-dB dynamic range at a 2-m position with an expectation of a long-distance target-detection range. The radar sensor has an 11.7-cm range resolution and is only $60\times 40\times $ 8 mm3 in size, with a weight of only 78 g. [ABSTRACT FROM AUTHOR]

It is well known that grid-feeding converters that synchronize to the grid through a Phase-Locked Loop (PLL) can become unstable after a fault. An often-neglected element that plays an important role in the converter synchronization stability is the PLL frequency limiter. While it slows down the phase change during the fault, the frequency limiter also constrains the error of the PLL input, thus leading to a longer settling time. This letter investigates the mechanism of the converter synchronization stability caused by the frequency limiter and provides a taxonomy to evaluate its impact on the overall system dynamic response. [ABSTRACT FROM AUTHOR]

This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer- $N$ phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, the proposed signal source shows a −73.1-dBc reference spur, −113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and −90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fsrms at 40.96 GHz and 122 fsrms (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is −3.24 dBm, and the power consumption is 372 mW. [ABSTRACT FROM AUTHOR]

When suffering the grid voltage distortion, the phase-locked loop (PLL) should equip with the fast response filter to precisely extract the fundamental voltage information for proper grid integration. To shorten the time delay induced by filters, this article proposes a new three-sample filter (TSF) to fast eliminate the harmonics of sampled grid voltage. Theoretically, it can filter out arbitrary individual harmonic with short time delay which could be as small as only two sampling periods. Moreover, TSF can reject a group of harmonics simultaneously within the specifically set time interval. The implementation issues of TSF as in-loop filter or prefilter for both three- and single-phase applications are demonstrated in synchronous reference frame PLL (SRF-PLL) SRF-PLL. Simulation and experimental results verified its advanced performance. [ABSTRACT FROM AUTHOR]

In recent years, microgrids (MGs) with renewable energy sources, diesel gen-sets, and droop-controlled converters have been increasingly used to guarantee the continuity of power supply in remote areas. Renewable energy sources have been typically connected to MGs by using an electronic converter that features the two controllers: a current-control loop and a phase-locked loop (PLL). Stability issues related to the PLLs application in electrical grids have already been addressed in the literature; however, dynamic interactions in MGs caused by PLLs have not been sufficiently explored. In this article, an MG that includes a grid-feeding voltage source converter and a grid-forming device (diesel gen-set or converter) is studied. All network elements are modeled analytically and the eigenvalue and participation-factor analyses are used to analyze the interactions between the devices. It is demonstrated that MGs formed by diesel gen-sets have reduced stability limits. Also, it is shown that stability margins of MGs formed by droop-controlled converters can be improved by changing the control parameters (e.g., PLL and internal controllers bandwidths). The main findings and conclusions are summarized and presented as a practical MG design guide. Theoretical results are validated in a lab environment comprising two 15 kW converters and one 75 kW grid emulator. [ABSTRACT FROM AUTHOR]

A second-order generalized integrator (SOGI) is a resonant regulator with a pair of complex-conjugate poles, and therefore, with infinite magnitude at its center frequency. Thanks to this property, one can put together a set of $m$ SOGIs in an elegant way and decompose a single-phase signal into its constituent frequency components and detect their amplitude and phase angle. Such a configuration, which is often referred to as the multi-SOGI (MSOGI) structure, requires a frequency estimator to adapt the center frequency of SOGIs to frequency changes. This frequency estimation is often provided by interconnecting the MSOGI structure with a basic frequency-locked loop (FLL) or phase-locked loop (PLL). The resulting structures are known as the MSOGI-FLL and MSOGI-PLL. These structures and their close variants are mathematically difficult to analyze probably because of the lack of a linear model for these systems. This article aims to bridge this research gap. First, it is shown how linear time-periodic (LTP) models of the MSOGI-FLL and MSOGI-PLL can be obtained. The model verification, obtaining open-loop harmonic transfer function from the LTP model, and LTP stability assessment of MSOGI-based synchronization systems are the next parts of this article. Finally, some close variants of the MSOGI-FLL/PLL are considered and their modeling and stability assessment are briefly discussed. [ABSTRACT FROM AUTHOR]

This article presents a 12–14.5-GHz fractional- ${N}$ subsampling phase-locked loop (PLL). Due to the subsampling topology, the noise in the subsampling phase detector (SSPD) and the subsampling charge pump (SSCP) is not multiplied by the divider ratio, improving the in-band phase noise. The multiphase generation required for the fractional- ${N}$ operation is implemented by both the digital-to-time-converter (DTC) and the phase interpolator to reduce the total delay required by the DTC, thereby suppressing the DTC intrinsic jitter. The proposed phase interpolator completely cancels out the short-current path by redefining the phase relationship between the input and the reset signal, improving its linearity significantly. The class-C voltage-controlled oscillator (VCO) consumes only 3.2 mW at 13.76 GHz while achieving −106-dBc/Hz phase noise at a 1-MHz offset. Designed and fabricated in 40-nm CMOS technology, the PLL operating in fractional- ${N}$ mode consumes 10.2 mW of power from a 1-V supply. The rms jitter integrated from 1 kHz to 100 MHz is 111 fs, arriving at a figure of merit (FoM) of −249 dB. [ABSTRACT FROM AUTHOR]

A 20-GHz fractional- ${N}$ analog phase-locked loop (PLL) leveraging a novel high-speed charge pump (CP) and an on-chip frequency reference is demonstrated. An on-chip fully integrable 2.5-GHz frequency reference using Texas Instrument’s indigenous bulk acoustic wave (BAW) resonator is demonstrated. The low noise high-frequency reference allows for significant lowering of the division modulus leading to enhanced suppression of CP, phase-frequency detector (PFD), and loop-filter (LF) noise. A low noise class-C transformer-coupled voltage-controlled oscillator (VCO) further allows for excellent jitter performance over wide integration bandwidths (BWs) while still working with a nominally low PLL loop BW. Capability is built into the design to characterize the PLL with either BAW or external reference. The design is implemented and fabricated in the GlobalFoundries 22-nm fully depleted silicon on insulator (FD-SOI) process. The class-C VCO is measured to be centered at $\sim $ 19.7 GHz with 16% tuning range (TR) while maintaining a flat $\vert {\rm FOM}\vert \sim $ 188 dBc/Hz (10-MHz offset) over the entire TR. The PLL measures an excellent jitter and $\vert {\rm FOM}_{j}\vert $ of 65/92 fs and $\sim $ 249/245 dB in integer/fractional modes, respectively. [ABSTRACT FROM AUTHOR]

A phase-locked loop (PLL) is commonly used in grid-connected power converter for synchronization. A single input single output (SISO) linear model of PLL with the phase angle of the point of common coupling (PCC) voltage as input and the estimated phase angle as the output is generally used in the PLL analysis and design. However, an undesirable coupling between the magnitude and phase of the input voltage is present when a filtering stage is incorporated before the control loop, which a SISO model cannot capture, and could result in a significant disturbance in the PLL estimated phase during grid faults. This paper proposes a generalized multi-input multi-output (MIMO) linear model that captures the complete PLL dynamics during symmetrical faults for a PLL equipped with any prefilter. Furthermore, a compensation method that decouples the magnitude dynamics of the input voltage from the phase dynamics is proposed in this paper. The proposed compensation improves the PLL's phase tracking performance by ensuring that the prefiltered PLL acts only on the PCC voltage phase changes. A vital application of the proposed compensation method for PLL is during a grid fault case, wherein the converters are expected to contribute to the fault current, which requires an accurate measurement of the PCC voltage phase. The compensation method's effectiveness is demonstrated using power hardware in the loop simulation of a hardware voltage source converter interfaced to a distribution system simulated in real-time. [ABSTRACT FROM AUTHOR]

An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper. The bootstrapped ring oscillator can boost the output voltage to a higher level than the supply voltage. Thus, the oscillator can be operated in low-supply-voltage applications. MOS varactor is used in the bootstrapped capacitor to reduce the area cost. Circuit analysis and simulated verification were performed for an optimized design. The interpolated DCO has multiphase outputs and a high operating frequency. The test chip was implemented in a 90-nm CMOS process, and the core area was $60\times 117\,\,\mu \text{m}^{2}$ . The power consumptions at 1160 MHz and 20 MHz were $912.6~\mu \text{W}$ (at 0.6 V) and $2.94~\mu \text{W}$ (at 0.2 V), respectively. In the worst-case jitter performance, the root mean square (RMS) jitters were less than 0.42%.

This paper proposed an improved full-order sliding-mode observer (IFSMO), applied to a sensorless control system of surface-mounted permanent magnet synchronous motor (SPMSM), to obtain a high-precision rotor speed and position. First, the IFSMO method, which combines the new sliding-mode function with the variable boundary layer function, is presented to suppress the chattering and accelerate the convergence speed of the system. Meanwhile, since the observer has the characteristics of a second-order low-pass filter, the high-frequency noise contained in the estimated back EMF signal can be effectively filtered out without an additional low-pass filter. Then, the proposed PLL is designed to obtain rotor position and speed. Finally, simulations and experiments of the SPMSM system based on the IFSMO method under different working conditions are implemented, which demonstrates the effectiveness of the proposed algorithm.

For synchronization between the grid voltage and generator voltage, we propose a phase-locked loop (PLL) algorithm with virtual rotational reference frame and feed-forward compensation. It is possible to accurately estimate the phase angle through a virtual coordinate system that uses the phase angle information of the grid instead of the phase angle information of the generator. In addition, to eliminate the effect of harmonic components, which make it difficult to calculate the exact phase angle and to alleviate the very sensitive problem to external noise, a feed-forward compensation algorithm is applied. To verify the feasibility of the proposed approach, PSIM simulations and experiments are performed on prototypes. In particular, in order to utilize the emergency generator as a demand resource, the existing stand-alone emergency generator system is changed to a grid-tied uninterruptible power supply structure and verified through a 280kW actual load test for four operating modes. With the proposed virtual coordinates and feed-forward compensation, fast and stable transfer switching is possible. The error of the phase angle estimation is excellent as 0.02°, and it has a 20% lower time-constant for phase angle estimation compared to the conventional method at the moment of phase transfer when 5% of the 5th harmonic component is included in the grid voltage. Consequently, it can be confirmed that inrush current do not occur in all operating modes.

The single-phase phase-locked loop (PLL) is essential for the stable operation and control of single-phase grid-connected converters. However, in practical applications, the grid voltage is usually affected by harmonics and dc offset, which will cause errors in the output of the PLL. Therefore, using sliding discrete Fourier transform filter (SDFT) as a prefilter, this paper proposes an improved single-phase synchronous reference frame PLL with a fixed sampling frequency, which can accurately and quickly obtain the grid parameters under distorted grid conditions. Most importantly, the paper theoretically analyzes phase and amplitude errors generated by SDFT for the first time and a quantitative compensation method is proposed, which is straightforward to be used by a reader. Finally, the proposed PLL is compared with other PLLs through simulation and experiments. The experimental results show the effectiveness and practicability of the proposed method.

Synchronverter (SV) control for distributed energy resources (DERs) is popular due to its capability of synchronous generator behavior emulation. Under an unbalanced grid, additional control strategy along with a higher order phase-locked loop (PLL) is generally integrated to SV control, for the injected power to be free from double-frequency ripples. Thus, the enhanced-PLL (EPLL) structure comprising positive, negative, and zero sequence control units is integrated to the standard SV in the proposed control, which results in ripple-free power injection by DER into an unbalanced grid. Further, the proposed control is capable of presynchronizing DER voltage to grid voltage, before connecting DER to the grid. Other significant benefits of the proposed control over existing SV-based methods for unbalanced grid are as follows: a) Integrating EPLL with SV yields a simple control structure, due to both being set in a natural frame; b) reduced number of parameters due to similarity between different sequence control units; c) simple implementation by using the low-pass filter of SV in the positive sequence control unit. Simulation and experimental results are presented to validate the presynchronization and ripple-free power injection by DER into an unbalanced grid for the proposed control. [ABSTRACT FROM AUTHOR]

The traditional power decoupling control of modular multilevel converter (MMC) is based on the phase synchronization achieved by the phase-locked loop (PLL), and MMC intricate inner dynamics are ignored, which jeopardizes the system stability and power decoupling. To improve the performance, a nonlinear phase-unsynchronized power decoupling control for MMC is proposed without PLL. At first, the MMC model as a nonlinear multi-input multi-output system is developed. The developed model illustrates that the MMC power coupling is caused by the ac current as well as the MMC capacitor voltages. Then, through the input–output linearization method, the proposed method decouples the MMC output powers without the phase synchronization. Involving integral control, the dynamics of MMC output powers are designed as second-order systems so that the control parameters can be easily determined based on the required transient performance. To verify the accuracy and correctness of the developed model, a comparison of MMC dynamics with the proposed control is conducted between the numerical solution in MATLAB and the EMT simulation in PSCAD/EMTDC. Moreover, seven cases in the EMT simulations and four cases in the experimental results demonstrate the desired phase asynchronization and power decoupling performance of the proposed method compared with the conventional $dq$ control. At last, the system zero dynamic stability is investigated and the influences of MMC control parameters, ac-side voltage, dc-side voltage and equilibrium points are analyzed to evaluate the stability performance of the proposed method. [ABSTRACT FROM AUTHOR]