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The design of ultra-low-voltage microcontroller (MCU) systems with high energy-efficiency operations is a key concept to achieve fully autonomous energy-harvesting powered Internet-of-Things applications. In this paper, a system-on-chip (SoC) is presented, embedding an ARM® Cortex®-M0+ MCU, $2 \times 4$ KB SRAM, an ultra-low power frequency synthesizer, a custom power switch, and a power management unit enabling the active and sleep modes. The 28 nm fully depleted silicon-on-insulator (FD-SOI) technology has been used to fabricate the device. The whole system operates at a fixed voltage of 0.5 V, and can switch from active and sleep/deep sleep modes, adjusting its frequency from 16 to 8 MHz or 32 kHz in one cycle upon energy availability. Silicon measurements report an SoC’s power consumption of 2.7 pJ/cycle at 16 MHz during active mode, and a total power consumption of 0.7 $\mu \text{W}$ during deep sleep mode. By combining frequency and power modes switching with extra reverse body-biasing, the system power consumption is drastically reduced by $2\times $ and $61\times $ in, respectively, sleep and deep sleep modes. [ABSTRACT FROM AUTHOR]

Ultra-low voltage operation is key to achieving energy-efficient operation for microcontroller (MCU) systems. Variation resiliency, high speed operation, and short design time are the most important challenges for these systems. This paper overcomes these challenges in a new design strategy that enables standard cell design with differential transmission gate logic. The commercial toolchain is extended with in-house developed add-ons and makes use of two custom libraries with different device lengths to allow high speed vs. low leakage trade-offs. The design flow is used to prototype two highly efficient 32-bit ARM Cortex-M0 MCU systems in 40-nm CMOS. The core of the first prototype scales down to 190 mV and 0.8-MHz and reaches 16.07 pJ/cycle at 31.2-MHz and 440 mV. The second prototype benefits from the dual libraries and reduces core energy consumption by 50% at the same speed performance. Minimum energy operation is thus achieved at an even lower voltage (370 mV) with the M0 core consuming only 8.80 pJ/cycle at 13.7-MHz, breaking the sub-10-pJ/cycle barrier for a 6–35-MHz range. [ABSTRACT FROM AUTHOR]

This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area. [ABSTRACT FROM AUTHOR]

Minimizing the energy consumption of battery-powered systems is a key focus in integrated circuit design. This paper presents an energy minimization loop, with on-chip energy sensor circuitry, that can dynamically track the minimum energy operating voltage of arbitrary digital circuits with changing workload and operating conditions. An embedded DC-DC converter which enables this minimum energy operation is designed to deliver load voltages between 0.25 V to 0.7 V. The minimum energy tracking loop along with the DC-DC converter and test circuitry were fabricated in a 65 nm CMOS process. The area overhead of the control loop is only 0.05 mm². Measured energy savings of the order of 50%-100% are obtained on tracking the minimum energy point (MEP) as it varies with workload and temperature. The DC-DC converter delivers load voltages as low as 250 mV and achieved an efficiency >80% while delivering load powers of the order of 1 μW and higher from a 1.2 V supply. [ABSTRACT FROM AUTHOR]

This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum VDD and VT to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum VDD for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-µm test chip is used to compare normal sizing and sizing to minimize operational VDD and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits. [ABSTRACT FROM AUTHOR]