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To overcome the nonlinear distortion inherent in analog ICs based on Si-MOSFETs, we report here the graphene-silicon hybrid analog amplifier ICs that integrate graphene field-effect transistor (GFET) and Si-MOSFET components. By fabricating homogeneous GFETs on a silicon wafer with prefabricated Si-MOSFETs, we obtained the hybrid ICs that neatly incorporate the high linearity of GFETs. The high-linearity analog amplifier ICs can thus be realized simply using basic MOSFET circuit configurations, without requiring complicated calibration designs. This hybrid integration principle may enable immediate practical applications of graphene electronics. [ABSTRACT FROM AUTHOR]

A simplified region-wise potential-based analytical model is established for boron (B) or nitrogen (N) substitution doped graphene field-effect transistor (GFET). The closed-form direct analytical relation between graphene channel potential and applied bias condition is developed by imposing the effective approximation for Fermi–Dirac integral function in various regions of operation. The boundary for distinct GFET operating regime is separated based on the position of Dirac point and Fermi energy level with respect to applied bias condition. The semiclassical drift and diffusive transport model is utilized to obtain the drain current. In addition to that, the drift component, diffusion coefficient, and its corresponding current component for B and N substitution doped GFETs have been modeled individually and their influence on total current is discussed. The proposed region-potential-based analytical model has shown good agreement with numerically solved self-consistent model. Also, the physical insights in device design, such as threshold voltage and saturation drain potential model with respect to various doping/device parameters, have been examined. [ABSTRACT FROM AUTHOR]

In this work, a new type of graphene ICs only comprising multiple graphene field-effect transistor (GFET) components is first reported. Based on the GFET design that enables homogeneous electrical characteristics in batch-made devices, the practicality and functionality significances of multi-GFET integration are experimentally demonstrated via high-fidelity amplifiers for baseband analog signals. Different from the quadratic relationship of the gate-controlled current output (in saturation region) in the traditional silicon-based MOSFETs, the saturation current output of GFETs relating to the gate-controls possesses high linearity. This advantage overcomes the inherent nonlinear distortion issues in the existing silicon MOSFET amplifiers and potentially provides a promising scenario for the accurate preamplification of weak analog signals. Besides, the novel circuit configuration and signaling principle may expand the developmental paradigm of analog amplifiers and set groundwork for the development and practicalization of advanced carbon-based nanoelectronic ICs. [ABSTRACT FROM AUTHOR]

A small-signal equivalent circuit for graphene field-effect transistors (GFETs) is proposed considering the explicit contribution of effects at the metal–graphene interfaces by means of contact resistances. A methodology to separate the contact resistances from intrinsic parameters, obtained by a deembedding process, and extrinsic parameters of the circuit is considered. The experimental high-frequency performance of three devices from two different GFET technologies is properly described by the proposed small-signal circuit. Some model parameters scale with the device footprint. The correct detachment of contact resistances from the internal transistor enables to assess their impact on the intrinsic cutoff frequency of the studied devices. [ABSTRACT FROM AUTHOR]

The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-reduced experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the trap effects on the channel potential within the device. High-frequency (HF) figures of merit and the intrinsic gain of the device obtained from both experimental and synthetic data with and without hysteresis show the importance of considering the generally overlooked impact of traps for analog and HF applications. [ABSTRACT FROM AUTHOR]

A unified quasi-ballistic transport model is developed for single- and double-gate graphene fieldeffect transistors (GFETs) using the McKelvey flux theory approach. The proposed model is compact, scalable, and compatible for the simulation of I-V characteristics of GFET for all regions of device operation. The drain current equation ( IDS) incorporates the formulation of quasithermal velocity, quasi-ballistic mobility of charge carrier (describe the carrier transportof 2-Dmaterial likegraphene), and source/drain backscattering coefficient. This model is also capable to describe the mobility of graphene material in degenerate and nondegenerate states. The GFET with different channel lengths, widths, and oxide thicknesses is simulated using this model for single- and double-gate devices.The proposedmodel synchronizedwith experimental results and explains the peculiar transport characteristics of GFET with normalized root-mean-square error less than 9%. [ABSTRACT FROM AUTHOR]

A thermally evaporated silicon monoxide (SiO) film has been experimented as the gate dielectric in graphene field-effect transistors (GFETs) due to its room-temperature and low-damage deposition without introducing chemical gases or ionized particles as in other film deposition techniques, which may cause damage to graphene. In order to evaluate the dielectric properties, a double-gated GFET was fabricated with a standard commercial thermally grown SiO2 layer as the bottom gate dielectric and thermally evaporated SiO as the top dielectric. The electrical characterizations revealed that the top-gate carrier mobility was 1081.3 cm2/Vs, reasonably comparable to the bottom-gate mobility. Furthermore, the breakdown strength of the SiO film reached 5.7 MV/cm, which was lower than that of the SiO2 dielectric (~10 MV/cm) but in the same order of magnitude. The breakdown mechanism of the SiO film was studied, and the current-voltage characteristics were in agreement with the Frenkel–Poole emission model. Finally, the relative dielectric constant of SiO was found to be 5.3, significantly higher than that of SiO2 (3.9). These results indicate that the thermally evaporated SiO can function as an excellent dielectric for graphene-based devices. [ABSTRACT FROM PUBLISHER]

We present the characterization of ballistic graphene field-effect transistors (GFETs) with an effective oxide thickness of 3.5 nm. Graphene channels are fully encapsulated within hexagonal boron nitride, and self-aligned contacts are formed to the edge of the single-layer graphene. Devices of channel lengths ( LG) down to 67 nm are fabricated, and a virtual-source transport model is used to model the resulting current–voltage characteristics. The mobility and source-injection velocity as a function of LG yields a mean-free-path, ballistic velocity, and effective mobility of 850 nm, 9.3\times 10^7 cm/s, and 13 700 cm2/Vs, respectively, which are among the highest velocities and mobilities reported for GFETs. Despite these best-in-class attributes, these devices achieve transconductance ( gm) and output conductance ( $g_{{\mathrm{ds}}}) of only 600 and 300 \mu \textS/\mu \textm , respectively, due to the fundamental limitations of graphene’s quantum capacitance and zero-bandgap. g_m values, which are less than those of comparable ballistic silicon devices, benefit from the high ballistic velocity in graphene but are degraded by an effective gate capacitance reduced by the quantum capacitance. The $g_{{\mathrm{ds}}}$ values, which limit the effective power gain achievable in these devices, are significantly worse than comparable silicon devices due to the properties of the zero-bandgap graphene channel. [ABSTRACT FROM PUBLISHER]

Through self-consistent quantum transport simulations, we evaluate the RF performance of monolayer graphene field-effect transistors in the bias region of negative output differential resistance. We show that, compared with the region of quasi-saturation, a voltage gain larger than 10 can be obtained, at the cost of a decrease in the maximum oscillation frequency of about a factor of 1.5–3 and the need for a careful circuit stabilization. [ABSTRACT FROM PUBLISHER]

We study theoretically the different transport behaviors and the electrical characteristics of a top-gated graphene field-effect transistor where boron nitride is used as the substrate and gate insulator material, which makes the ballistic transport realistic. Our simulation model is based on the Green's function approach to solving a tight-binding Hamiltonian for graphene, self-consistently coupled with Poisson's equation. The analysis emphasizes the effects of the chiral character of carriers in graphene in the different transport regimes including the Klein and band-to-band tunneling processes. In particular, the Klein tunneling is shown to have an important role on the onset of the current saturation which is analyzed in detail as a function of the device parameters. Additionally, we predict the possible emergence of negative differential conductance and investigate its dependence on the BN-induced bandgap, the temperature, and the gate insulator thickness. Short-channel effects are evaluated from the analysis of transfer characteristics as a function of gate length and gate insulator thickness. They manifest through the shift of the Dirac point and the appearance of current oscillations at short gate length. [ABSTRACT FROM AUTHOR]

We present a study on the metal–graphene contact properties. Utilizing a dual-gate field-effect transistor device, an energetic separation between the Fermi level and the Dirac point in the contact areas can be adjusted deliberately by applying an appropriate front-gate voltage that acts only on the channel. This front-gate voltage is compensated by an opposite large-area back-gate voltage, thereby mimicking the metal induced doping effect. A back-gate voltage sweep enables identifying two distinct resistance peaks—a result of the combined impact of the graphene cones in the contact and in the channel region. Comparing our experimental data with simulations allows extracting the coupling strength between metal and graphene and also estimating the magnitude of the metal-induced doping concentration in the case of palladium contacts. In contrast to conventional metal–semiconductor contacts, our simulations predict a decreased on-current for increased coupling strength in graphene field-effect transistors. [ABSTRACT FROM PUBLISHER]

This letter presents a detailed study of transport in graphene field-effect transistors (GFETs) with various channel lengths, from 5 \mu\m down to 90 nm, using transferred graphene grown by chemical vapor deposition. An electron–hole asymmetry observed in short-channel devices suggests a strong impact from graphene/metal contacts. In addition, for the first time, we observe a shift of the gate voltage at the Dirac point in graphene devices as a consequence of gate length scaling. The unusual shift of the Dirac point voltage has been identified as one of the signatures of short-channel effects in GFETs. [ABSTRACT FROM AUTHOR]