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The sufficiency of electricity market competition and the economy of power system operation require that the economic dispatch should not only preserve the bus privacy but consider network losses. The existing economic dispatch methods, however, can’t preserve the privacy of each bus from leakage and even complicate the solution when they reasonably consider network losses, due to the coupling complexity of network losses. To address these issues, this paper presents a novel distributed economic dispatch (DED) method based on KKT optimality conditions and iteration functions. It focuses on an economic dispatch model that contains bus active power balance equations and generator power limit inequalities. First, the model’s KKT optimality conditions with inequalities are simplified to equivalent pure equality-type optimality conditions. Then a set of iteration functions is created using the Taylor series, which overcomes the difficulty caused by the fact that unknown bus voltage phases are completely contained in the sine and cosine functions of optimality conditions. Finally, a fast fixed-point iteration procedure is proposed for bus agents to solve the economic dispatch model. The proposed method reasonably considers network losses by using the set of bus active power balance equations. It not only preserves the privacy of each bus from leakage but is straightforward in solution (does not complicate the solution). In addition, it is fully bus-level distributed. Numerical simulation results of systems with different sizes verified the effectiveness and advantages of the proposed method.

Closed-loop experiments involving biological and artificial neural networks would improve the understanding of neural cells functioning principles and lead to the development of new generation neuroprosthesis. Several technological challenges require to be faced, as the development of real-time spiking neural network emulators which could bear the increasing amount of data provided by new generation High-Density Multielectrode Arrays. This work focuses on the development of a real-time spiking neural network emulator addressing fully-connected neural networks. This work presents a new way to increase the number of synapses supported by real-time neural network accelerators. The proposed solution has been implemented on the Xilinx Zynq 7020 All-Programmable SoC and can emulate fully connected spiking neural networks counting up to 3,098 Izhikevich neurons and 9.6e6 synapses in real-time, with a resolution of 0.1 ms.

Multiplier-free adaptive equalizers are significant for improving utilization, reducing costs, and ensuring robustness in real-time hardware implementation. In this letter, we demonstrate that using only one bit shift and one XOR operation to replace a real multiplier is a feasible and low-complexity way to obtain a multiplier-free parallel fixed-point adaptive equalizer (PFAEQ). The performances of the multiplier-free PFAEQ (MF-PFAEQ) are verified by a 112 Gbits/s polarization multiplexing quadrature phase shift keying (PM-QPSK) back-to-back experiment. It can be found that, under different parallels and different bit width of signals, MF-PFAEQ shows similar performances to traditional PFAEQ. Besides, in some cases, compared with the traditional PFAEQ, MF-PFAEQ also shows the similar convergent speed. In addition, according to the Quartus 15.0 synthesis, compared to traditional PFAEQ, the logic utilization and total registers of MF-PFAEQ reduce by 51.8% and 45.2%, respectively. This study is novel in using rather less shift operations to obtain a multiplier-free adaptive equalizer. [ABSTRACT FROM AUTHOR]

Energy flow calculation (EFC) plays an important role in steady-state analysis of multi-energy systems (MESs). However, the independent management of sub-energy systems (subsystems) poses a considerable challenge to solve the high-order nonlinear energy flow model due to the limited information exchange between these subsystems. In this article, a fixed-point based distributed method is proposed for EFC in an electricity-gas-heating system. Firstly, the mathematical modeling of each subsystem with coupling units is introduced. Then, two information exchange structures among subsystems are presented as sequential and parallel structures. Based on the fixed-point theorem, novel distributed sequential and parallel methods for EFC are proposed to calculate energy flow distribution in MESs. In our proposed method, the EFC in subsystems is implemented by the individual system operators, with limited information exchange between subsystems. Therefore, the information privacy of subsystems can be preserved in this solution process. Moreover, the convergence of the proposed method is guaranteed, and the sufficient conditions for the convergence are presented. Lastly, simulations on a MES demonstrate the effectiveness of the proposed method and the quantified superiority over the existing methods in computation time, accuracy and reliability. [ABSTRACT FROM AUTHOR]

We present a hardware-based implementation of linear program (LP) decoding for binary linear codes. LP decoding frames error–correction as an optimization problem. In contrast, variants of belief propagation (BP) decoding frame error–correction as a problem of graphical inference. LP decoding has several advantages over BP-based methods, including convergence guarantees and better error-rate performance in high-reliability channels. The latter makes LP decoding attractive for optical transport and storage applications. However, LP decoding, when implemented with general solvers, does not scale to large blocklengths and is not suitable for a parallelized implementation in hardware. It has been recently shown that the alternating direction method of multipliers (ADMM) can be applied to decompose the LP decoding problem. The result is a message-passing algorithm with a structure very similar to BP. We present modifications to this algorithm, resulting in a more intuitive and hardware-compatible form. This is particularly true for projection onto the parity polytope: the major computational primitive for ADMM-LP decoding. Furthermore, we present results for a fixed-point Verilog implementation of ADMM-LP decoding. This implementation targets a field-programmable gate array (FPGA) platform to evaluate error-rate performance and estimate resource usage. We show that frame error rate performance well within 0.5 dB of double-precision implementations is possible with 10-bit messages. Finally, we outline research opportunities that should be explored en route to an application-specific integrated circuit (ASIC) implementation that is capable of Gigabit-per-second throughput. [ABSTRACT FROM AUTHOR]

Linear Time Invariant (LTI) filters are often specified and simulated using high-precision software, before being implemented in low-precision fixed-point hardware. A problem is that the hardware does not behave exactly as the simulation due to quantization and rounding issues. This article advocates the construction of LTI architectures that behave as if the computation was performed with infinite accuracy, then converted to the low-precision output format with an error smaller than its least significant bit. This simple specification guarantees the numerical quality of the hardware, even for critical LTI systems. Besides, it is possible to derive the optimal values of all the internal data formats that ensure that the specification is met. This requires a detailed error analysis that captures not only the quantization and rounding errors, but also their infinite accumulation in recursive filters. This generic methodology is detailed for the case of low-precision LTI filters in the Direct Form I implemented in FPGA logic. It is demonstrated by a fully automated and open-source architecture generator tool, and validated on a range of Infinite Impulse Response filters. [ABSTRACT FROM AUTHOR]

Numerical uncertainties from noisy inputs or finite-precision roundoff errors are unavoidable on resource-constrained systems. While techniques exist to compute worst-case bounds on these errors for arithmetic operations, these approaches do not generalize to programs which take discrete decisions. In this case, the more interesting quantity is the probability of the program making the wrong decision. In this paper, we study two approaches to compute a guaranteed bound on this probability: 1) exact probabilistic inference and 2) probabilistic static analysis. By themselves, they provide accuracy and scalability, respectively, but unfortunately not at the same time. We propose an extension to the latter approach which allows us to bound the probability tightly and fully automatically while scaling to small but interesting embedded examples. [ABSTRACT FROM AUTHOR]

Reliance on object or people detection is rapidly growing beyond surveillance to industrial and social applications. The histogram of oriented gradients (HOG), one of the most popular object detection algorithms, achieves high detection accuracy but delivers just under 1 frame/s on a high-end CPU. Field-programmable gate array (FPGA) accelerations of this algorithm are limited by the intensive floating-point computations. All current fixed-point HOG implementations use large bit width to maintain detection accuracy, or perform poorly at reduced data precision. In this paper, we introduce the full-image evaluation methodology to explore the FPGA implementation of HOG using reduced bit width. This approach lessens the required area resources on the FPGA, and increases the clock frequency and hence the throughput per device through increased parallelism. We evaluate the detection accuracy of the fixed-point HOG by applying state-of-the-art computer vision pedestrian detection evaluation metrics and show it performs as well as the original floating-point code from OpenCV. We then show our single FPGA implementation achieves a $68.7 \times $ higher throughput than a high-end CPU, $5.1 \times $ higher than a high-end graphics processing unit (GPU), and $7.8 \times $ higher than the same implementation using floating-point on the same FPGA. A power consumption comparison for different platforms shows our fixed-point FPGA implementation uses $130 \times $ less power than CPU, and $31 \times $ less energy than GPU to process one image. [ABSTRACT FROM PUBLISHER]

Many power update functions proposed in the literature are functions of the effective interference (the ratio of the interference to the path gain). It is well known that for an upper-bounded wide-sense standard power update function (which is either standard or type-II standard function for each user), there exist a unique fixed-point and its convergence to its unique fixed-point is guaranteed. However, depending on the corresponding objective function, there exist power update functions which do not have the properties of monotonicity and scalability for all values of the effective interference (i.e., they are not wide-sense standard). For such a non-wide-sense standard power update function, the value-region of the effective interference for each user may be divided into several sub-regions, for each of which, a different wide-sense standard power update strategy may be employed, which we call it as a piece-wise wide-sense standard function. In this letter, we show that a bounded piece-wise wide-sense standard function is two-sided scalable and thus it poses a unique fixed-point and its convergence to its corresponding fixed-point is guaranteed. [ABSTRACT FROM PUBLISHER]

Fixed-point arithmetic datapaths with heterogeneous scaling and wordlengths are commonplace in resource, latency, or power constrained designs. This paper describes and proves correct a formal method for accurate high-level casting of optimal adders and subtractors. The proposed approach allows for an early accurate estimation of resource usage which is then available for high-level decision-taking in the design flow. As a result, decoupling between high-level and low-level synthesis is achieved. Results concerning the impact of the approach on resource estimates and a discussion on the wide applicability of the method are presented. [ABSTRACT FROM PUBLISHER]

This paper describes a single-cycle throughput lighting accelerator fabricated in 1.05 V, 32 nm CMOS for on-die acceleration of 3D graphics vertex and pixel shading in high-performance processors and mobile systems-on-chip. Log-domain parallel computation of ambient, diffuse, and specular lighting using high-accuracy 32b log and anti-log units that convert computation from floating-point (FP) to fixed-point domain, 32b sparse-tree fixed-point adders and a 32\,\times\, 32b signed fixed-point multiplier with truncated partial product reduction tree enable 2.05 GVertices/s throughput measured at 1.05 V, 25\,^\circ\C in an area of 0.064 mm^2 while achieving: (i) 47% reduction in critical path logic stages compared to previously published work, (ii) 0.56% mean vertex lighting error compared to single-precision FP computation, (iii) 354 \mu\W active leakage power measured at 1.05 V, 25\,^\circ\C, (iv) scalable performance up to 2.22 GHz, 232 mW measured at 1.2 V, (v) peak energy-efficiency of 56 GVertices/s/W, measured at 560 mV, 25\,^\circ\C, and (vi) 119.6 dB PSNR for a 2 M pixel high-resolution 3D image. [ABSTRACT FROM AUTHOR]

Mixed-scaling-rotation (MSR) coordinate rotation digital computer (CORDIC) is an attractive approach to synthesizing complex rotators. This paper presents the fixed-point error analysis and parameter selections of MSR-CORDIC with applications to the fast Fourier transform (FFT). First, the fixed-point mean squared error of the MSR-CORDIC is analyzed by considering both the angle approximation error and signal round-off error incurred in the finite precision arithmetic. The signal to quantization noise ratio (SQNR) of the output of the FFT synthesized using MSR-CORDIC is thereafter estimated. Based on these analyses, two different parameter selection algorithms of MSR-CORDIC are proposed for general and dedicated MSR-CORDIC structures. The proposed algorithms minimize the number of adders and word-length when the SQNR of the FFT output is constrained. Design examples show that the FFT designed by the proposed method exhibits a lower hardware complexity than existing methods. [ABSTRACT FROM PUBLISHER]

This brief paper proposes a new algorithm to train interpolation Gaussian radial basis function (RBF) networks in order to solve the problem of interpolating multivariate functions with equally spaced nodes. Based on an efficient two-phase algorithm recently proposed by the authors, Euclidean norm associated to Gaussian RBF is now replaced by a conveniently chosen Mahalanobis norm, that allows for directly computing the width parameters of Gaussian radial basis functions. The weighting parameters are then determined by a simple iterative method. The original two-phase algorithm becomes a one-phase one. Simulation results show that the generality of networks trained by this new algorithm is sensibly improved and the running time significantly reduced, especially when the number of nodes is large. [ABSTRACT FROM AUTHOR]

This paper investigates the application of computational methods via Satisfiability Modulo Theory (SMT) to the bit-width allocation problem for finite precision implementation of numerical calculations, specifically in the context of scientific computing where division frequently occurs. In contrast to the large body of work targeted at the precision aspect of the problem, this paper addresses the range problem where employing SMT leads to more accurate bounds estimation than those provided by other analytical methods, in turn yielding smaller bit-widths, and hence a reduction in hardware cost and/or increased parallelism, while maintaining robustness as is necessary for scientific applications. [ABSTRACT FROM AUTHOR]

Many applications in real-time signal, image, and video processing require automatic algorithms for rapid characterizations of signals and images through fast estimation of their underlying statistical distributions. We present fast and globally convergent algorithms for estimating the three-parameter generalized gamma distribution (G Γ D). The proposed method is based on novel scale-independent shape estimation (SISE) equations. We show that the SISE equations have a unique global root in their semi-infinite domains and the probability that the sample SISE equations have a unique global root tends to one. The consistency of the global root, its scale, and index shape estimators is obtained. Furthermore, we establish that, with probability tending to one, Newton-Raphson (NR) algorithms for solving the sample SISE equations converge globally to the unique root from any initial value in its given domain. In contrast to .existing methods, another remarkable novelty is that the sample SISE equations are completely independent of gamma and polygamma functions and involve only elementary mathematical operations, making the algorithms well suited for real-time both hardware and software implementations. The SISE estimators also allow the maximum likelihood (ML) ratio procedure to be carried out for testing the generalized Gaussian distribution (GGD) versus the G Γ D. Finally, the fast global convergence and accuracy of our algorithms for finite samples are demonstrated by both simulation studies and real image analysis. [ABSTRACT FROM AUTHOR]

The paper proposes a new fixed-point method for solving time-stepping hysteretic field problems. The method is aimed to speed up the convergence of the fixed-point solution and enhance the applicability of the fixed-point iteration. The method makes use of the differential reluctivity and produces a locally convergent solution. A 1-D finite-element procedure is performed to test the method by computing the magnetic field in a ferromagnetic laminated steel. The efficiency, stability, and applicability of the method are assessed in which the method is proven simple and remarkably fast. [ABSTRACT FROM AUTHOR]

A procedure for obtaining tighter bounds on zero-input limit cycles is presented. The proposed new bounds are applicable to digital filters of arbitrary order, described in state-space formulation and implemented with fixed-point arithmetic. For the most part, we obtain smaller bounds than those reported in the literature, using a computationally efficient algorithm that is easy to implement and has a comparatively short execution time. Simulation results show the validity of the proposed theory. [ABSTRACT FROM AUTHOR]

We propose a novel methodology for estimating the shape parameter of a generalized Gaussian distribution (GGD). This new method is based on a simple estimating equation derived from a convex shape equation. The estimating equation is completely independent of gamma and polygamma functions. Thus, no lookup table, interpolation, or additional subroutine to evaluate these functions are required for real-time implementations of the proposed method, which is in contrast to all existing methods. Furthermore, we establish that the has a unique global root on the positive real line and the Newton-Raphson root-finding algorithm converges to the unique global root from any starting point in a semi-infinite interval Θmin. More importantly, we show that the sample-based shape estimating equation has a unique global root with probability tending to one and the root is consistent for the true shape parameter. we prove via fixed point arguments that, with probability tending to one, the Newton-Raphson algorithm converges to the unique global root of the sample shape estimating equation from any starting point in Θmin. Some numerical experiments are also provided to demonstrate the global convergence and the excellent finite sample performance of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a 64-bit fixed-point vector multiply-accumulator (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 64 x 64, two 32 x 32, four 16 x 16, or eight 8 x 8 bit signed/unsigned multiply-accumulates using essentially the same hardware as a scalar 64-bit MAC and with only a small increase in delay. The scalar MAC architecture is "vectorized" by inserting mode-dependent multiplexing into the partial product generation and by inserting mode-dependent kills in the carry chain of the reduction tree and the final carry-propagate adder. This is an example of "shared segmentation" in which the existing scalar structure is segmented and then shared between vector modes. The vector MAC is area efficient and can be fully pipelined, which makes it suitable for high-performance processors and, possibly, dynamically reconfigurable processors. The "shared segmentation" method is compared to an alternative method, referred to as the "shared subtree" method, by implementing vector MAC designs using two different technologies and three different vector widths. [ABSTRACT FROM AUTHOR]

Editor's note:Data representation is an important problem for scientific computing problems that are mapped to FPGAs. The key challenge here is to derive best trade-offs between precision and performance. This article describes methods to manage the complexity associated with the analysis of data representation techniques so that we thereby understand precision/performance trade-offs.—Krishnendu Chakrabarty, IEEE Design & Test editor in chief [ABSTRACT FROM PUBLISHER]