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As a novel signal control method, signal Cooperative Control with traffic Supply and Demand (CCSD) is superior to the traditional control methods and could satisfy the control requirements under all traffic conditions. However, the optimization solution of CCSD cannot meet the real-time control requirement for its exhaustive search. To overcome the problem, in this paper, the optimization problem of CCSD is reconstructed by the time-varying traffic supply and demand, and the problem is reduced as a problem of space search. Then, the krill herd (KH) algorithm is introduced and employed to realize the fast solution of CCSD (named KH-CCSD). During the process of optimization, the search space representation and fitness function for the KH algorithm are constructed to satisfy the solution of CCSD. The optimal signal timing plan is obtained by an iterated search of krill swarm in a multi-dimensional time-varying space cooperatively constrained by traffic supplies and demands. The convergence and effectiveness of KH-CCSD are validated by comparing experiments, in which the convergence of KH-CCSD is tested by different initializations and KH-CCSD is compared with the Webster method and capacity-aware back-pressure (CABP) control under unsaturated, saturated, and oversaturated conditions. The experiments results show that KH-CCSD performs a fast convergence and KH-CCSD is superior to the Webster method and CABP. As a result, KH-CCSD could satisfy the application of CCSD under all traffic conditions.

Traffic signal control is widely used at intersection to improve its operation efficiency. However, the existing signal control systems cannot satisfy the control requirements under unsaturated, saturated, and oversaturated conditions, which will induce queue spillover, even network deadlock. A signal Cooperative Control method with traffic Supply and Demand (CCSD) on a single intersection is put forward to maximize the efficiency and avoid queue spillover by the cooperation between traffic supply and demand. A general CCSD control framework is constructed by the control relationship description and discrete-time statespace equations. Furthermore, the uniform matrix description of CCSD is put forward under the framework to fast solve the problem by matrix calculation. An artificial intelligence planning model on CCSD is established by an objective function compromising between throughput and fairness to satisfy the control requirements under dynamic unknown traffic environment. CCSD is compared with the Webster method and capacity-aware back-pressure (CABP) control in the experiments by both the simulation data and investigation data under unsaturated, saturated, and oversaturated conditions. The results show that CCSD is superior to CABP control and the Webster method in the throughput, the number of stops, and stop time, and can avoid the queue spillover. Accordingly, CCSD can be used to improve the efficiency and avoid queue spillover at intersection under all traffic conditions.

Memristors with small size, fast speed, low power, CMOS compatibility and nonvolatile modulation of device resistance are promising candidates for the next-generation data storage and in-memory logic computing paradigm. In comparison to the binary logics enabled by memristor devices, multi-valued logics can provide higher computation efficiency with simple operation scheme, reduced circuit complexity, and smaller chip area. In this contribution, we demonstrate that all the 27 univariate ternary logic operations can be realized with a single ZnO three-state resistive switching memristor in at most three steps. The nonvolatile modulation characteristics of the memristor allow the read step to be independent of the logic operation and capacitate logic-in-memory applications. The present methodology could be beneficial for constructing future high-performance computation architectures. [ABSTRACT FROM AUTHOR]

In-memory computing based on memristive logic is considered as a prospective non von Neumann computing paradigm. In this letter, we systematically analyze the four-variable logic method and map it into the operation of two anti-serial complementary memristors in the crossbar array architecture. Arbitrary Boolean logic can be implemented within three cycles with the experimental evidence of reconfigurable NAND, NOR, and XOR logic using Pt/HfO2/TiN devices. Taking advantage of the functional flexibility, a parallel 1-bit full adder that can be realized in 8 cycles within a $\textsf {4}\times \textsf {3}$ array has been designed and verified in simulation. [ABSTRACT FROM AUTHOR]

In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 107 cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture. [ABSTRACT FROM AUTHOR]

Nonvolatile stateful logic through RRAM is a promising route to build in-memory computing architecture. In this letter, a logic methodology based on 1T1R structure has been proposed to implement functionally complete Boolean logics. Arbitrary logic functions could be realized in two steps: initialization and writing. An additional read step is required to read out the logic result, which is in situ stored in the nonvolatile resistive state of the memory. Cascade problem in building larger logic circuits is also discussed. Our 1T1R logic device and operation method could be beneficial for massive integration and practical application of RRAM-based logic. [ABSTRACT FROM PUBLISHER]