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Convolutional neural network (CNN) has demonstrated great success in pattern recognition scenarios at the cost of nearly billions of parameters and consequent convolution operations. Various dedicated hardware designs are proposed to accelerate the CNN computation in more energy-efficient manners. Especially, the bit-serial accelerator (BSA) is one of the most effective approaches on resource-limited platforms by eliminating zero-bit computations. However, the irregular distribution and varying number of effectual (nonzero) bits in weights significantly cause hardware underutilization, impeding further performance improvement of state-of-the-art BSAs. To address this issue, BitCluster, a hardware-friendly quantization method, is proposed to make each weight with the identical number of effectual bits for load-balanced computation. Considering distinct sensitivities to weight precision in different neural layers, layer-level BitCluster is proposed to design further for fine-grained weight quantization. It systematically determines the layerwise quantization configurations, which significantly improve the overall performance with <1% accuracy loss. BitCluster is comprehensively evaluated on a BitCluster-compatible BSA design by taking six mainstream CNN models as benchmarks. The experimental results show that the BitCluster-based BSA achieves $1.6\times $ higher hardware utilization and $3.4\times $ speedup on average than state-of-the-art BSAs, with $5\times $ better energy efficiency on average. [ABSTRACT FROM AUTHOR]

In this article, a quantized network acceleration processor (QNAP) is proposed to efficiently accelerate CNN processing by eliminating most unessential operations based on algorithm-hardware co-optimizations. First, an effective-weight-based convolution (EWC) is proposed to distinguish a group of effective weights (EWs) to replace the other unique weights. Therefore, the input activations corresponding to the same EW can be accumulated first and then multiplied by the EW to reduce amounts of multiplication operations, which is efficiently supported by the dedicated process elements in QNAP. The experimental results show that energy efficiency is improved by 1.59 $\times $ –3.20 $\times $ compared with different UCNN implementations. Second, an error-compensation-based prediction (ECP) method adopts trained compensated values to replace partly unimportant partial sums to further reduce potentially redundant addition operations caused by the ReLU function. Compared with SnaPEA and Pred on AlexNet, 1.23 $\times $ and 1.75 $\times $ higher energy efficiencies (TOPS/W) are achieved by ECP, respectively, with marginal accuracy loss. Third, the residual pipeline mode is proposed to efficiently implement residual blocks with a 1.5 $\times $ lower memory footprint, a 1.18 $\times $ lower power consumption, and a 13.15% higher hardware utilization on average than existing works. Finally, the QNAP processor is fabricated in the TSMC 28-nm CMOS process with a core area of 1.9 mm2. Benchmarked with AlexNet, VGGNet, GoogLeNet, and ResNet on ImageNet at 470 MHz and 0.9 V, the processor achieves 117.4 frames per second with 131.6-mW power consumption on average, which outperforms the state-of-the-art processors by 1.77 $\times $ –24.20 $\times $ in energy efficiency. [ABSTRACT FROM AUTHOR]

Face detection and alignment are two fundamental tasks for facial applications and the corresponding accelerators have been designed to enable energy-efficient acceleration. However, these dedicated accelerators are always designed separately, thereby ignoring the inherent correlation between face detection and alignment and causing additional communication and area overhead. Based on this motivation, a multi-task cascaded convolutional networks (MTCNN) algorithm-based accelerator is presented in this work to support both face detection and alignment for multiple faces. First, multiply-accumulate (MAC) operations and memory access of the magnification process in the resize module are reduced by 22.8% and 24.8% on average, respectively, when compared with those of similar methods. Second, clustering non-maximum suppression (C-NMS) is proposed to significantly reduce the intersection over union computation and eliminate the hardware-inference sorting process in NMS, yielding a 16.0% speedup in the overall process. Third, an efficient pipeline architecture is proposed to implement a complexity- and memory-intensive proposal network of MTCNN in a more computationally efficient manner, with 38.3% less memory capacity than a similar solution. Meanwhile, only approximately half of the multipliers are needed to achieve the same throughput with high pipeline utilization. Fourth, considering the variable number of faces in each input, a batch schedule mechanism is proposed to improve the fully-connected layer hardware utilization by 16.7% on average in the batch process. Based on a simulation with the TSMC 28 nm CMOS process, this accelerator consumes only 10.9ms at 400 MHz to simultaneously process 5 faces. The power efficiency reaches 4.80 TOPS/W, which is $227.4\times $ higher than that of the state-of-the-art solution. [ABSTRACT FROM AUTHOR]

The coarse-to-fine shape searching (CFSS) framework is a recently developed algorithm that achieves relatively high accuracy in face alignment by alleviating the poor initialization problem facing traditional cascaded regression approaches. However, its high computational complexity and memory access demands make it difficult for CFSS to satisfy the requirements of real-time processing. To address this issue, a fast shape searching face alignment (F-SSFA) accelerator is presented based on the optimization of the CFSS algorithm and an efficient hardware implementation. First, the learning-based low-dimensional speeded-up robust features method, based on the correlations between the SURF features and the regression targets, is introduced to distill the feature set down to the only most distinct features to reduce the computing load. Second, the partial keypoints Euclidean distance and shape affine transformation are introduced to replace feature extraction and support vector machine classification, thereby accelerating the shape searching process. Compared with CFSS, F-SSFA achieves a $5.8\times $ speedup while achieving similar accuracy. Moreover, a VLSI architecture is proposed to realize the fixed-point F-SSFA algorithm. Multiple descriptors located in adjacent regions are simultaneously generated in a single access to the corresponding image data. Therefore, repeated memory access operations are avoided. The optimal parameter configuration for hardware implementation is also exploited based on a tradeoff between accuracy and hardware performance. Simulated with TSMC 65-nm 1P8M technology within a 3.6 mm2 area, a post-layout simulation shows that 700 fps can be achieved while consuming 300 mW at 200 MHz. [ABSTRACT FROM AUTHOR]

Considering that the binary-feature-based approximate nearest neighbor (ANN) search technique has not been fully exploited to date, a multisegment binary feature-based hierarchical clustering tree model is proposed to achieve fast binary feature matching (FM). In addition, the multisegment vocabulary forest, is developed for the ease of hardware-oriented implementation. During the ANN searching process, the corresponding leaf nodes of each segment of the query feature are returned simultaneously to improve processing speed and accuracy. Furthermore, a hierarchical decomposition based on the term frequency-inverse document frequency is used to reduce the run-time search space and total memory footprint for object database storage. Finally, a fine-grained feature-level fully pipelined object recognition accelerator is implemented based on a dedicated design between FM and object scoring. The performance of the proposed object recognition accelerator is evaluated based on TSMC 65 nm CMOS technology. The accelerator achieves 22 M-vec/s and $6.8 \boldsymbol \times 10^{\mathbf {8}}$ vec/J in throughput and energy efficiency for full-HD resolution, respectively; these results represent a $10.6\boldsymbol \times $ and $9\boldsymbol \times $ improvement, respectively, relative to current state-of-the-art solutions. The average power consumption is 32.6 mW when operating at 200 MHz. [ABSTRACT FROM AUTHOR]

Face alignment is a critical task in many multimedia and vision applications that use face-based algorithms. Recent research has focused on achieving efficient initialization to improve performance; however, the use of facial attributes and the extent of their correlation with initialization have not been fully exploited. This paper presents a lightweight method called expression- and pose-based adaptive initialization (EXPAI), in which facial attributes, that is, expression and pose information, are used as priors. This approach can significantly improve the face alignment performance. In addition, reliable expression and head pose information can be derived simultaneously in the same framework. First, an expression- and pose-based template dictionary is formed by augmenting the mean shape across three degrees of freedom, thereby substantially improving the robustness of the initial shape with respect to large head pose variations. Second, each the template corresponds to an image of interest, which is jointly determined using a shape-constrained multiclass classifier and binary classifiers, and is assigned a pretrained confidence coefficient. The initial shape that is thus generated for subsequent cascaded regression is more adaptive and enables higher accuracy. Furthermore, EXPAI enables initialization with significantly increased computational efficiency because of its independence from the original dataset. The experimental results obtained on the widely used 300-W dataset show that our method achieves very competitive performance compared with that of state-of-the-art methods. In particular, for the challenging subset of 300-W, EXPAI reduces errors by more than 14% compared with coarse-to-fine shape searching (CFSS), which currently exhibits the best performance among regression-based approaches. Furthermore, a speed increase of more than 10 times compared with CFSS is achieved. [ABSTRACT FROM AUTHOR]

Binary image descriptors, which derive image feature description from the local image patches directly, are widely adopted in the mobile and embedded applications due to lower computational complexity and memory requirement. With the aim of improving the computation efficiency without degrading recognition performance, a lightweight binary robust descriptor is proposed based on the analysis of the state-of-the-art binary descriptors in this paper. A directional edge detection and optimized keypoint score function are developed to refine the keypoints. In addition, rotation invariance is achieved by executing circular symmetric-based descriptor generation and a coarse-grained orientation calculation method concurrently. The experimental results demonstrate that the proposed keypoint detector and binary descriptor achieve more than two times speedup and at least 23.6% improvement in processing speed with comparable performance, respectively. Furthermore, a very large scale integration architecture is also designed based on in-depth exploration of bit-level and task-level parallelism. Based on the postlayout simulation in a TSMC 65-nm CMOS process, the accelerator can achieve 135 frames/s on 1080p image while only consuming 87.5 mW at a 200-MHz operating frequency. [ABSTRACT FROM PUBLISHER]

Mobile device-centric multi-device collaborative computing has been proved as an optimal alternative, which satisfies the mobile users? increasing expectations towards richer people-centric computing services on mobile platforms. However, many non-smart embedded devices, which are characterized by poor processing power and limited wireless network connection capabilities, are not utilized effectively in current collaborative computing paradigm yet. In this paper, a universal mobile platform, Ver-Comp (Versatile Companion), with a dedicated processor, wireless connectivity and customized mobile OS (Operating System), is proposed to serve as the smart companion device of various non-smart electronic devices (such as digital camera, printer, electronic toy, microwave oven, heart rate monitor and etc.). Non-smart embedded electronic devices are therefore turned to be smart objects so as to cooperate with current smart mobile devices or cloud platforms seamlessly. The processing capabilities of current smart mobile devices are thus augmented indirectly and their battery lives are also extended significantly by migrating partial tasks to the smart objects. In order to meet the requirements of high energy efficiency and quick boot time, an uneven-dual-core architecture processor with multi-OS support is proposed. Furthermore, a Multipleclient Raindrop File System (MRFS) and a File Allocation Table eXtension (FAT-X) file system are also developed to make the data synchronization and virtual access across multiple heterogeneous computing platforms easy and flexible. Finally, three fascinating applications are implemented to demonstrate the flexibility and promising usage of the proposed platform. [ABSTRACT FROM AUTHOR]