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The developing optimization algorithms provide promising solutions for speeding up analog integrated circuit sizing. However, the optimization of complicated circuits whose solution regions are narrow remains to be a challenge. With a limited number of sampling points due to the restriction of computational resources, it is difficult for traditional algorithms to achieve satisfactory results for such circuits. To solve this problem, this article proposes a rule-guided genetic algorithm (RG-GA) for analog circuit optimization. Different from the random mutation approach in the traditional genetic algorithm (GA), the RG-GA introduces a design rule-guided mutation (RGM) mechanism which helps to find the solution region in a more straightforward fashion. Instead of handing over circuit optimization tasks to pure mathematical algorithms, the proposed method takes advantages of valuable design knowledge to improve searching efficiency. This novel algorithm is implemented and deployed to design a two-stage rail-to-rail operational amplifier (OPA), an LC voltage controlled oscillator (LC-VCO) and a four-stage OPA. Experimental results show that compared to the traditional GA method, the RG-GA achieves about 1.5 and 3.3 times speed enhancement for the two-stage rail-to-rail OPA and the LC-VCO, respectively. For the four-stage OPA, the RG-GA method can find an acceptable point within the given number of iterations while the traditional GA could not. [ABSTRACT FROM AUTHOR]

This article presents a new analog circuit optimization system for automated sizing of analog integrated circuits. It consists of a genetic algorithm (GA)-based global optimization engine and an artificial neural network (ANN)-based local optimization engine. The key new idea is to use parallel computation to train ANN models for design space neighborhoods thus the local minimum search (LMS) can have a much faster search speed. For the GA-based global optimization, circuit performances are calculated by parallel SPICE simulations. For the LMS, circuit performance data are derived from ANN model predictions instead of SPICE simulations. Since the most time for an ANN-based LMS is spent on SPICE calls which can be run in parallel, the LMS process can also exploit the multiple core configuration of a modern computational server in addition to the GA global search. The fully parallelized optimization system is deployed to design a two-stage rail-to-rail operational amplifier and a fifth-order active-RC Chebyshev complex band-pass filter. The experimental results show that the proposed method provides about four times speed enhancement and comparable results compared with traditional approaches employing the same parallel global optimization but sequential SPICE calls during LMS. [ABSTRACT FROM AUTHOR]

A hybrid low-dropout regulator (LDO) with exponential-ratio array (ERA) and analog based transient voltage compensation is implemented in 65-nm CMOS. The hybrid LDO (HLDO) is capable of reducing a voltage drop upon load change by more than 70%, and the ERA enables fast tracking time, enlarging dynamic range of the digital loop. The HLDO achieves 99.7% current efficiency with the output dynamic range of 0.01-to-40 mA (4000x) and obtains the transient output voltage drop of 55 mV for a load current jump of 0.55 mA from 20 $\mu \text{A}$. When both the dynamic and the static performances are considered, the proposed HLDO shows the state-of-the-art performance among other recent digital LDOs and HLDOs. [ABSTRACT FROM AUTHOR]

This paper describes a frequency-domain on-off keying (F-OOK) modulation method which utilizes power detection of both a carrier and a sideband by modulating the carrier frequency with a pre-selected modulation template. Compared to on-off keying and binary frequency-shift keying modulations, more efficient bandwidth control is achieved for the same data rate with a symmetric FM template. Since the proposed modulation maintains the average center frequency of the carrier regardless of data pattern, the F-OOK signal can be generated by using only the high-pass modulation path of the conventional phase-locked loop-based two-point modulator, thus relaxing design complexity. A prototype transmitter implemented in 65-nm CMOS consumes 1.9 mW from a 0.8-V supply with a data rate of 750 kb/s, achieving an energy efficiency of 2.5 nJ/b. [ABSTRACT FROM AUTHOR]

This paper describes a short-range transceiver architecture using frequency-hopped sinusoidal OOK pulses. Since signal bandwidth does not necessarily have to satisfy >500 MHz requirement like conventional ultra-wideband (UWB) pulses, the proposed transceiver named as a very-wide band (VWB) transceiver offers degrees of freedom to choose an optimum operation duty cycle in terms of energy efficiency, bandwidth efficiency, and communication range, while providing much lower operation duty cycle than that of narrow band OOK transceiver. The VWB transmission significantly relaxes the complexity of transceiver design without requiring advanced CMOS technology. In the transmitter, pulse generation circuit design is simplified with the duty-cycled sinusoidal signal compared to that in the impulse-radio UWB (IR-UWB) transmitter. In the receiver, an asynchronous energy detection topology is proposed to achieve robust energy detection by overcoming the synchronization issue as well as the saturation problem of the integrator circuit. A prototype 3-to-4 GHz VWB transceiver is implemented in 0.18 \mu \textm CMOS. The transceiver achieves the communication distance of >2 m at 1 Mb/s data rate with the peak-to-peak pulse amplitude of only 300 mV and the duty cycle of 0.6%, consuming 0.42 mW from a 1.8 V supply. [ABSTRACT FROM PUBLISHER]