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This paper discusses the efforts to shrink the micro-bump pitch to $20\ \mu\mathrm{m}$ and then $10\ \mu\mathrm{m}$ with solder micro-bumps for silicon-on-silicon 3D assembly by leveraging alternate solder diffusion barrier metals and tuning the assembly process to realize both good yield and reliable interconnects. Specifically in this paper, the assembly process challenges are detailed and the impact of our barrier metal assessment and process optimization to resolve these technical challenges are discussed through the study of solder joint reliability results using internal $20 \mu \mathrm{m}$ pitch and $10\ \mu\mathrm{m}$ pitch solder micro-bump test-vehicles (TV).

Flip chip process excels due to its low cost, fine pitch, small form factor and its ready-adaptation to the conventional Surface Mount Technology (SMT) process, in the fact that the reflow is often used to form the solder joint. As the use of Pb free solder is legislated today, it is vital to understand the impact of reflow process conditions on the formation of the flip chip solder joint, so that the assembly process of the flip chip can be better controlled. This paper introduces a comprehensive experimental study on the impact of Pb free reflow profile parameters towards flip chip on silicon assembly solder joint formation characteristics as well as the reliability performance. The reflow parameters studied include the soak time, peak temperature and time above liquidus. Three levels of each reflow parameter are investigated. The Response Surface Methodology (RSM) is used for Design of Experiment (DOE) to explore the quadratic effect of the investigated parameters. Results studied include the package assembly yield, package shear strength, intermetallic compound thickness as well as the package reliability performance. Study results show that the fine pitch flip chip on silicon package has a wide reflow process window to achieve 100% yield, if reflowed in a Nitrogen environment. Yield loss was found when the packages are reflowed in air. With the fifteen reflow profiles studied, it was found that the reflow parameters are not significant in terms of the package shear strength. For the intermetallic compound thickness, it was found that the time above liquidus is a significant factor, with a 99.9% confidence level. No statistical difference was found among packages assembled under different reflow conditions up to 2500 liquid to liquid thermal shock reliability testing.

Market demand is increasing for even higher packaging densities, smaller size, lower cost, and more heterogeneous functionality. As a result, three dimensional (3D) packaging has emerged as a leading packaging solution. This paper introduces a 3D Wafer Level CSP packaging architecture that provides a cost effective, rapid time to market alternative to emerging 3D die to wafer integration technologies.

A new low cost 3 dimensional wafer level chip scale package (3D-WLCSP) technology that leverages the existing infrastructures of wafer level packaging and high volume flip chip assembly is presented. This paper provides an overview of the new 3D-WLCSP technology including flip chip on wafer bonding assembly technologies required to produce the 3D face to face flip chip on wafer package. Development efforts are focused on high density flip chip placement forming the 3D-WLCSP and the associated innovations that this type of packaging and assembly includes. In this work, the flip chip pitch and bump size is varied as well as key assembly materials (including fluxes and underfills) used to attach the flip chip to the WLCSP. Processing innovations developed include flip chip fluxing methods for very fine pitch and small bump sizes, vision recognition of the chip and substrate during assembly, reflowing of the flip chips on a wafer, and underfilling a solder balled WLCSP wafer with chip components in close proximity. Initial reliability results are presented which highlight that even though the flip chip is mounted silicon to silicon, the pitch and bump size make it so that the underfill selection has a large impact on the reliability of the assembly. Various aspects of the die to wafer assembly process are explored including scaling issues with high volume assembly, utilization of low cost underfill approaches such as no flow underfills and wafer applied underfills, and underfill encroachment on the WLCSP balls. Flux and underfill material combinations are identified that enable high assembly yields and provide reliable 3D-WLCSP assemblies with respect to liquid to liquid thermal shock testing and unbiased autoclave aging.