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The Class Φ2/EF2 amplifier is an attractive topology for high-voltage and high-frequency power conversion because of the high efficiency, reduced device voltage stress, simplicity of gate driving, and load-independent ZVS operation. Due to many degrees of freedom for tuning, previous studies can only solve the single-ended Φ2 circuit using numerical methods. This work focuses on improving the design and operating characteristics of a push–pull Φ2 amplifier with a T network connected between the switch nodes, or a PPT Φ2 amplifier. The PPT Φ2 amplifier has less circulating energy and achieves higher cutoff frequency ƒT than other Φ2/EF2 circuits. We, then, present a series-stacked input configuration to reduce the switch voltage stress and improve the efficiency and power density. A compact 6.78-MHz, 100-V, 300-W prototype converter is demonstrated that uses low-cost Si devices and achieves 96% peak total efficiency and maintains above 94.5% drain efficiency across a wide range of voltage and power. Together with the advances in wide-bandgap semiconductors and magnetic materials, the PPT Φ2 circuit opens more possibilities for the state-of-the-art performance of solid-state RF amplifiers in high-frequency, high-power applications, including wireless charging for electric vehicles, plasma RF drives, and nuclear magnetic resonance spectroscopy. [ABSTRACT FROM AUTHOR]

One benefit of switching a converter at very high frequencies—even to the multimegahertz range—is that the loop bandwidth can be increased so that the transient performance is significantly improved. However, using the conventional small-signal model of continuous conduction mode (CCM) for quasi-square-wave (QSW) converters introduces a huge mismatch for the placement of the dominant poles when compared to the experiment results. The double poles in high-frequency QSW converters are split widely which cannot be predicted by the conventional model. A modified small-signal model of the QSW flyback converter is proposed to predict the double-pole splitting phenomenon and to analytically quantify the damping effect. The impacts of deadtime on control-to-output transfer function have been investigated in detail. The conventional CCM model turns out to be a special case of the proposed model. The theoretical analyses were eventually verified by Simplis simulation and experimental results on a 5-MHz QSW flyback converter. [ABSTRACT FROM AUTHOR]

In cloud computing, with full control of the underlying infrastructures, cloud providers can flexibly place user jobs on suitable physical servers and dynamically allocate computing resources to user jobs in the form of virtual machines. As a cloud provider, scheduling user jobs in a way that minimizes their completion time is important, as this can increase the utilization, productivity, or profit of a cloud. In this paper, we focus on the problem of scheduling embarrassingly parallel jobs composed of a set of independent tasks and consider energy consumption during scheduling. Our goal is to determine task placement plan and resource allocation plan for such jobs in a way that minimizes the Job Completion Time (JCT). We begin with proposing an analytical solution to the problem of optimal resource allocation with pre-determined task placement. In the following, we formulate the problem of scheduling a single job as a Non-linear Mixed Integer Programming problem and present a relaxation with an equivalent Linear Programming problem. We further propose an algorithm named TaPRA and its simplified version TaPRA-fast that solve the single job scheduling problem. Lastly, to address multiple jobs in online scheduling, we propose an online scheduler named OnTaPRA. By comparing with the start-of-the-art algorithms and schedulers via simulations, we demonstrate that TaPRA and TaPRA-fast reduce the JCT by 40-430 percent and the OnTaPRA scheduler reduces the average JCT by 60-280 percent. In addition, TaPRA-fast can be 10 times faster than TaPRA with around 5 percent performance degradation compared to TaPRA, which makes the use of TaPRA-fast very appropriate in practice. [ABSTRACT FROM AUTHOR]

A design methodology is introduced to select a minimum core volume for an inductor or coupled inductors experiencing appreciable core loss. The geometric constant (Kgac) has been found to be a power function of the core volume for commercial toroidal, ER, and PQ cores, permitting the total loss to be expressed as a direct function of the core volume. The inductor is designed to meet specific loss or thermal constraints. An iterative procedure is described in which 2-D or 3-D proximity effects are first neglected and then subsequently incorporated via finite-element simulation. The methodology is demonstrated for coupled inductors in a 5-MHz converter in critical conduction mode. The core loss is verified using rectangular excitation and the winding loss is inferred from thermal measurements. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel analysis method for divisible load scheduling in mesh, torus and Gaussian network, a new type of interconnection network that has the same node degree as the mesh and torus, but shorter network diameter and shorter average hop distances under equal network size. The divisible scheduling in these three networks are uniformly formulated as the Maximum Finish Time Minimization (MFTM) problem. It involves minimizing the makespan of the load distribution and processing. The MTFM problem, a relaxed MFTM problem, a linear programming problem version and a heuristic algorithm are described and solved. The first three of these problems have identical solutions. The heuristic algorithm is close in performance to the optimal solution, significantly outperforms the previously described dimensional algorithm, and has much wider application range than the previously proposed phase algorithm. [ABSTRACT FROM PUBLISHER]

The recently proposed optical cut-through (OpCut) switch holds a great potential in achieving high energy efficiency, as it allows optical packets to cut through the switch in optical domain whenever possible, which avoids power-hungry O/E/O conversion. In the OpCut switch, to ensure in-order transmission, only optical Head-of-Line (HOL) packet of a switch flow, i.e., the stream of packets sharing the same input and output port, is allowed to cut-through the switch, and optical HOL packets are always prioritized over buffered HOL packets to achieve high cut-through ratio, which is measured by the portion of packets cutting through the switch optically. However, under such priority rule, switch flows with buffered packets are at the risk of starvation, and the OpCut switch fails to achieve 100 percent throughput for all admissible i.i.d. traffics due to the unfairness in packet scheduling. To address this two issues, in this paper we propose a delay threshold rule for packet scheduling, in which buffered packets with delays exceeding a preset delay threshold are prioritized over optical packets. In the meanwhile, the cut-through ratio is very low under heavily congested traffic due to maintaining packet order, whereas the Internet is designed to accommodate a certain degree of packet reorder, which is very common in practice due to path multiplicity. In this paper, we design a bounded-reorder packet scheduling algorithm that significantly increases the cut-through ratio of the OpCut switch while allowing a small degree of out-of-order transmission. Our extensive simulation results show that the energy efficiency of OpCut switch can be significantly improved with only a very small degree of packet reordering, which has little adverse impact on the network application performance. [ABSTRACT FROM PUBLISHER]

The ever increasing intra-chip and inter-chip traffic load in computing systems has been pushing traditional electronic interconnects to their limit in communication bandwidth, latency, and energy consumption. In order to achieve the high bandwidth and low latency required by intra-chip and inter-chip communications and mitigate the high interconnect power dissipation, optical interconnects have been considered as a promising candidate for intra-chip and inter-chip interconnections in next generation computing systems. In addition, packet switching is an efficient switching paradigm to fully utilize the communication bandwidth. However, due to lack of random access optical memory, it is challenging to implement all-optical packet switching in optical interconnects. In this paper, we exploit bufferless routing, a special type of packet-switching, to overcome the problem of lack of random access optical buffer. More specifically, we study bufferless routing in a novel optical multichip system, called Gaussian macrochip, where embedded chips are interconnected by an optical Gaussian network. By taking advantage of the underlying Hamiltonian cycles in the Gaussian network, we design a bufferless routing algorithm for the Gaussian macrochip, which routes packets along the shortest path in the absence of deflection, and guarantees that deflected packets reach their destinations within N hops. Our extensive simulation results demonstrate that by adopting the proposed routing algorithm, Gaussian macrochip can support much higher inter-chip communication bandwidth, has much shorter average packet delay, and is more power efficient than the previously proposed architectures for optical multichip systems. [ABSTRACT FROM AUTHOR]

With the development of multiprocessor system on chips (MPSoCs), it is expected that hundreds of computing cores will be operating on a single chip in the near future. This will require high-performance on-chip networks with very low latency to provide a communication substrate for the increasing number of cores. In this paper, we consider Gaussian on-chip networks that are of significant topological advantages over traditional mesh and torus networks in terms of diameter and average hop distance. Many applications on MPSoCs need global data movement and global control to exchange data and synchronize the execution among cores, which require all-to-all broadcast communication. In this paper, we propose an all-to-all broadcast algorithm suitable for on-chip implementation on the Gaussian network topology. The algorithm utilizes controlled message flooding based on a broadcast pattern, which can be described in a formal, generic way for each node in terms of a few simple operations and can be easily built into router hardware. Furthermore, the generic broadcast pattern also ensures a balanced traffic load in all dimensions in the network so that minimum total latency for all-to-all broadcast can be achieved. The algorithm overlaps message switching time with transmission time in a pipelined fashion to further reduce the total communication latency of all-to-all broadcast. Comparison results demonstrate the topological merits of Gaussian networks and ultralow latency of the proposed all-to-all broadcast algorithm. [ABSTRACT FROM AUTHOR]