108 results on '"Zamboni, M."'
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2. A Reconfigurable Array Architecture for NML
3. Design of NML Circuits based on M-RAM
4. Out-of-plane NML modeling and architectural exploration
5. Logic-in-Memory: A Nano Magnet Logic Implementation
6. Logic-in-Memory architecture made real
7. A Technology Aware Magnetic QCA NCL-HDL Architecture
8. Domain Magnet Logic (DML): A new approach to magnetic circuits
9. A standard cell approach for MagnetoElastic NML circuits
10. Physical design and testing of Nano Magnetic architectures
11. Fault tolerant nanoarray circuits: Automatic design and verification
12. Design challenges of an UWB system for breast cancer detection
13. Automatic Place&Route of Nano-magnetic Logic circuits
14. Biosequences analysis on NanoMagnet Logic
15. On the functional test of the BTB logic in pipelined and superscalar processors
16. Protein alignment HW/SW optimizations
17. Silicon nanoarray circuits design, modeling, simulation and fabrication
18. ToPoliNano: A synthesis and simulation tool for NML circuits
19. Magnetic QCA Majority Voter feasibility analysis
20. ToPoliNano: Nanoarchitectures design made real.
21. Nanofabric power analysis: Biosequence alignment case study.
22. A flexible simulation methodology and tool for nanoarray-based architectures.
23. MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture.
24. The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology.
25. A Low-power CMOS 2-PPM Demodulator for Energy Detection IR-UWB Receivers.
26. A 1-bit Synchronization Algorithm for a Reduced Complexity Energy Detection UWB Receiver.
27. UWB Receiver Design and Two-Way-Ranging Simulation using VHDL-AMS.
28. A multiprocessor based packet-switch: performance analysis of the communication infrastructure.
29. Design and implementation of a scalable multimedia processor.
30. FPGA power efficient inverse lifting wavelet IP
31. Power bus optimal sizing in presence of power supply noise
32. Automated power supply noise reduction via optimized distributed capacitors insertion.
33. Switching noise analysis framework for high speed logic families.
34. Low-cost IP-blocks for UMTS turbo decoders.
35. Speed and behaviour improvement for semidynamic flip-flop logic family.
36. VLSI Reed Solomon decoder architecture for networked multimedia applications.
37. Cell library development using multi-objective function optimization.
38. Noise safety design methodologies.
39. A 50 Mbit/s iterative turbo-decoder.
40. Transistors optimization of CMOS logic structures for high performance IC.
41. A noise test structure for CMOS logic families.
42. A CMOS power-delay model for CAD optimization tools
43. Logic-in-Memory: A Nano Magnet Logic Implementation.
44. New 2 Gbit/s CMOS I/O pads.
45. A statistical noise-tolerance analysis and test structure for logic families.
46. A 650 MHz pipelined MAC for DSP applications using a new clocking strategy.
47. Design and validation with HDL Verilog of a complex input/output processor for an ATM switch: the CMC.
48. Pandora-a microprogrammable node for DSP oriented architectures.
49. Executing contextual logic programming on a dedicated VLSI coprocessor.
50. A 500 MHz 2d-DWT VLSI processor.
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