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The three-dimensional flow of Water based Graphene Oxide (GO-W) and Ethylene Glycol based Graphene Oxide (GO-EG) nanofluids amongst the binary upright and parallel plates is considered. The unsteady movement of the nanofluid is associated with the porous medium and the uniform magnetic field is executed in the perpendicular direction of the flow field. The basic governing equations have been altered using the Von Karman transformation, including the natural convection in the downward direction. The solution for the modeled problem has been attained by means of optimal homotopy analysis method (OHAM). The influence of the physical parameters on the momentum boundary layer, pressure, and temperature fields is mainly focused. Moreover, the comparison of the GO-W and GO-EG nanofluids under the impact of physical constraints has been analyzed graphically and numerically. The imperative physical constraints of the drag force and heat transfer rate have been computed and discussed. The results have been validated using the error analysis and the obtained outcomes have been shown and discussed. The obtained results are compared with the numerical ND-Solve method. It is obtained that the increasing order of the iterations reduces the absolute error and the results go to the strong convergence. Moreover, the impact of the physical parameters is more precise in the GO-EG nanofluid due to its higher thermophysical properties.

In this work buried channel devices were successfully integrated in HKMG. Analog, noise and reliability performance have been reported and compared to a surface device. The devices were processed to have the same V Tsat for the nominal geometry of a corresponding surface device. Advantages and drawbacks of the two integrations are discussed and explained with the support of calibrated TCAD simulations.

The paper presents a TCAD modeling approach of the 28nm HKMG ESF3 Flash Cell. The methodology encompasses both DC and transient simulations with focus on hot carrier injection modeling. The ensuing Floating Gate Spacer optimization presents the trade-off between the various figures of merit and highlights the need for a comprehensive DC/transient simulation approach during Flash cell optimization.

This paper presents the characterization and reliability results achieved on 1.8 V 4 Mb flash array built around 3rd generation Embedded SuperFlash® (ESF3) memory cell featuring high-k metal gate (HKMG) select transistor and embedded into Low-Power 28 nm CMOS HKMG technology with gate-first architecture. Endurance shows better performance in terms of erase degradation as compared to prior technology nodes with poly-SiON select transistor. This improvement is attributed to HKMG-related process integration scheme allowing to reduce the effect of the CMOS baseline on tunnel oxide quality. Excellent program-erase performance, program disturb windows and data retention capability are observed.

Gate tunable graphene-metal hybrid nanoantenna is proposed here with detailed numerical simulations carried out to evaluate the absorption of multi-layer graphene nanoantenna at terahertz frequencies, specifically at far-infrared. The investigated graphene nanoantenna composes of multi-layer graphene stack formation, which is placed above the gold hexagon radiator to efficiently couple activated graphene plasmons. The efficient coupled plasmons between graphene layers and gold hexagon increase the absorption of the antenna. Furthermore, the relationship between the absorption and multi-layer graphene is analysed by changing the Fermi energy of the graphene sheet, thus providing tunability of broadband absorption at a wide range of frequencies. The investigated nanoantenna has a resonant frequency at 30.5 THz with a bandwidth of 0.6 THz, while the trilayer graphene nanoantenna results in better absorption almost reaching 100% with a bandwidth of 2.5 THz. The simulation of the graphene-metal antenna is performed in CST studio by using an FDTD solver. The designed antenna has various utilizations in the field of photonics i.e. terahertz imaging, sensing, and spectroscopy applications.

An effective design for self-protection medium voltage nMOS with modification of drain junction in 28nm high voltage CMOS technology is presented. Pull down nMOS of the output driver is the main electrostatic discharge path. Design of Source/Drain junction of baseline device can be optimized for only current driving ability and DC reliability. Sometimes this design is not sufficient as ESD protection device including Self-protection output driver device which can be possible long-term reliability issue after ESD stress. Modification of N+ drain junction with LDD spacer mask shows improved ESD performance by reducing the electric field at poly/drain overlap region and, spreading the ESD current path between drain and source. TLP, HBM, DC-IV and, HCI characterization techniques were used to verify the structure and, TCAD simulations were used to examine failure analysis.

A new substrate integrated waveguide (SIW) based leaky wave antenna (LWA) is presented in this paper for backward endfire (-90°) radiation. Measured gain at backward endfire is 12.1 dBi. To verify the simulated results, a prototype is fabricated. The proposed antenna is well suited for applications including unmanned aerial vehicles (UAVs), modern RADAR systems, directional communication systems, modern missiles and self-driving cars etc.

This paper proposes three methods of reducing device gate resistance and parasitic capacitance while boosting transconductance of MOSFET on 22FDX®. The f MAX can be improved by 50% and up to 75% for NFET and PFET with respect to a standard 2.0µm finger width layout, respectively.

The paper describes manufacturing process and layout optimizations to improve RF performance of 22FDX® N/PFET devices, based on a comprehensive calibration of DC and RF figures of merit. Process and Device simulations of the individual and combined elements show ft/fmax improvement up to about 1.13/1.1x (NFET) and about 1.32/1.24x (PFET) over standard devices mainly driven by mechanical stress and parasitic R/C elements.

Trauma is the major cause of death in metropolises and it becomes even worse in developing countries, due to the huge delay between incident occurrence and patient arrival at the emergency center. Among others, a key contributing factor is the inefficient notification system that lacks essential information to the rescue services in a real-time manner. This paper describes an application framework for emergency event reporting system. The proposed approach is based on crowdsourcing that utilizes participatory sensing to leverage multiple smartphones users to collectively report emergency events. Volunteers within the vicinity of an incident can promptly trigger an alert notification to the rescue services with crucial information such as location coordinates, type of incident and number of victims. The system process this information and sent alert to the ambulance and other rescue services with optimized route details and the location of nearest emergency centers. This proposed framework found to be more efficient and comprehensive than conventional systems thus can be useful for future smart cities.

A comparison of CMOS devices with best in class noise behavior and low power consumption for analog/mixed signal applications has been achieved by extensive TCAD simulations. The intrinsic gain gm/ID of FDSOI transistors was optimized by several process adjustments. An advanced bulk device with improved noise behavior was used as a reference and different bias conditions were simulated. With certain layer optimizations the gm/ID was improved by 50% in the low power regime. An additional improvement up to 50% has been achieved by biasing the FDSOI device in double gate mode (DGM).

The impact of device geometry, process integration and back bias on Low-Frequency Noise (LFN) performance of 22FDX® thin oxide devices has been investigated. Calibrated TCAD simulations were used to clarify the role of carrier distribution on LFN. More than 20% (30%) gate bias power spectrum density S Vg reduction is demonstrated in thin (thick) oxide devices with an appropriate choice of device construction and bias.

We demonstrate for the first time the integration of the proven SuperFlash® bit cell into 28 nm High-K Metal Gate (HKMG) technology, incorporating logic HKMG into the flash cell. Flash cell and high-voltage (HV) devices are implemented into a cost-optimized process flow saving seven masks compared to other 28nm eFLASH technologies. Comparable program/erase (P/E) endurance of up to one million cycles at 125°C is shown and program disturb characteristics meets array operation requirements. The Wordline transistor exhibits no degradation in sub-threshold slope of the post 100k P/E cycling, demonstrating robust reliability despite the introduction of HKMG into the flash cell. Additionally, the HKMG based HV devices demonstrate performance similar to platforms without HKMG material.

22nm FDSOI is an excellent technology for IOT SOC RF/mmWave applications because of low complexity and cost, low voltage libraries, and high RF/mmWave performance [1]–[2]. SOC applications require require high voltage devices for on chip power management (e.g. back gate bias generation), IO transistors, sensor drivers, and off chip output drivers. These integrated circuits need technologies with high breakdown voltage $(\mathrm{B}\mathrm{V}_{\mathrm{d}\mathrm{s}\mathrm{s}})$, and low on-resistance $(\mathrm{R}_{\mathrm{D}\mathrm{S}\mathrm{o}\mathrm{n}})$. For switching and RF applications these devices also need to have high $f_{\mathrm{T}}$ and $f_{\mathrm{M}\mathrm{A}\mathrm{X}}$. In this paper RFLDMOS devices integrated into a 22nm FDSOI technology are described. The RFLDMOS devices include 3. 3V, 5. 0V, and 6.5V RFLDMOS devices. These devices have been stressed and pass 10 year life time. The 3. 3V RFLDMOS devices have $55\mathrm{G}\mathrm{h}\mathrm{z}f_{\mathrm{T}}$, 65 GHz $f_{\mathrm{M}\mathrm{A}\mathrm{X}}, 9.6\mathrm{V}\mathrm{B}\mathrm{V}_{\mathrm{d}\mathrm{s}\mathrm{s}}$, and 1.16 mOhm$\star$mm2 $\mathrm{R}_{\mathrm{D}\mathrm{S}\mathrm{o}\mathrm{n}}$. The 6. 5V RFLDMOS devices have 41GHz $f_{\mathrm{T}}$, 69 GHz $f_{\mathrm{M}\mathrm{A}\mathrm{X}}$, 12. $2\mathrm{V}\mathrm{B}\mathrm{V}_{\mathrm{d}\mathrm{s}\mathrm{s}}$, and 1. S6 mOhm$\star$mm2 $\mathrm{R}_{\mathrm{D}\mathrm{S}\mathrm{o}\mathrm{n}}$. These devices represent the best reported $\mathrm{B}\mathrm{V}_{\mathrm{d}\mathrm{s}\mathrm{s}}, \mathrm{R}_{\mathrm{D}\mathrm{S}\mathrm{o}\mathrm{n}},f_{\mathrm{T}}$ and $f_{\mathrm{M}\mathrm{A}\mathrm{X}}$ for any RFLDMOS in an advanced node $(\lt 28\mathrm{n}\mathrm{m})$ technology.

This paper presents a 0.110um2Ultra Low Leakage (ULL) 6T-SRAM for Internet Of Things (lOT) application with competitive 0.7pA/cell retention leakage and $\pmb{1.45}\mathbf{mV}^{\ast}\mathbf{um}$ transistor mismatch coefficient (AVT). A back gate doping method to control the sub-threshold leakage is demonstrated on 22FDX™ (a 22nm FDSOI technology), which increases VT while maintaining the same AVT as compared to the case with no back gate doping. We demonstrate extremely low retention voltage (Vret) capability down to 0.35V on a 32Mb SRAM array with a corresponding SRAM VDD domain retention leakage of 0.9uA/Mb at 0.5V.

In this paper, a comparative study of microstrip patch antenna using microstrip line feed and coaxial feed is proposed. Rogers RT5880 is used as a substrate on which metal patch is mounted. The designed antenna resonates at 9.3 GHz (Radar frequency X band). Design is simulated using computer simulation technology. The proposed antenna has Voltage Standing Wave Ratio (VSWR) of 1.258 and 1.485, Gain of 7.622 dB and 7.548 dB, Directivity of 7.850 dBi and 7.773 dBi and radiation efficiency of 94.89% and 94.95% with return loss of −18.9dB and −14.209 dB for Microstrip line feed and coaxial feedrespectively.

This paper presents a micro strip patch antenna for future 5G-communication technology at centered frequency 38GHz and 54GHz having bandwidth 1.94GHz and 2GHz respectively with low cost substrate and small size patch best suited for miniaturized devices. It consists of Rogers RT5880 (lossy) substrate with dielectric constant 2.2 with loss tangent of 0.0013 and standard thickness 0.508mm, PEC patch and PEC ground. Substrate of dimensions 6mm×6.25mm and patch with dimensions 2mm×2mm is used. Microstrip-line feeding technique is used. Array having 4 elements with 4mm spacing has been proposed to achieve 12 dB gain for mobile data Applications on millimeter wave frequencies at 38.6GHz, 47.7GHz and 54.3GHz having bandwidth 3.5GHz, 2.5GHz and 1.3GHz respectively with Tapered line feeding. Overall size of antenna is 6mm×6.25mm×0.578mm. The proposed Antenna design is simulated on CST Microwave Studio.

Fluid flow and heat transfer of an isothermal cylinder in the wake of another of different diameters in tandem arrangement is numerically simulated at a Reynolds number Re = 200 and Prandtl number, Pr = 0.71. The diameter, d, of upstream cylinder is changed while diameter, D, of downstream cylinder is kept constant. Transient two-dimensional simulations are carried at various range of diameter ratios (d/D = 0.24, 0.4, 0.6, 0.8, 1.0) and spacing ratio (distance from center of upstream cylinder to forward stagnation point of downstream cylinder) L =5.5d. It is found that both cylinders shed vortices for 0.4 ≤ d/D ≤1.0, two prominent vortex shedding frequencies are detected in the wake of downstream cylinder, one represent the primary Karman vortex street, and other with large vortical structures having low frequency evolved due to merging of vortices in the wake, nomenclature as secondary vortex street. With decrease in d/D, the frequency of secondary vortex street is increased, while vortices getting stronger. Novel tertiary frequencies are also found in the spectrum of Nusselt number, involved in the heat transfer enhancement with decrease in d/D. Based on the numerically simulated results heat transfer around isothermal cylinder is classified into three different regions, characterized by impingement of vortices from upstream cylinder, shear layer characteristics and correlation of vortex evolution in the near wake. Heat transfer is enhanced for d/D ≥ 0.4, both cylinders lies in the co-shedding regime, standing vortices in the reattachment regime have a curtailing tendency with respect to heat transfer at d/D =0.24. Heat is transported by vortical structures in the wake.