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Radio-frequency interference (RFI) problems in modern electronic product become complex which result in the increasing number of scanning points. Conventional near-field phaseless source reconstruction methods such as double planes iteration method and single plane iteration method will spend a lot of time in both scanning and calculating. To save the calculating time and scanning time, an alternating iterative method is proposed for source reconstruction based on magnitude-only and single-plane near field scanning. Firstly, the single-plane scanning data is divided into two groups as group A and B according to the components, i.e. the electric field group and the magnetic field group for the four components, or ${H_{x}}$ group and ${H_{y}}$ group for two components. Then, the processed A and B phaseless data groups are used iteratively in the back-and-forth transformations to get the equivalent dipole elements. Under the premise of a large amount of scanning data, such as the simulation example, compared with conventional method filling the scanning data into a whole matrix, the proposed method can save 90% calculating time, especially the time in singular value decomposition (SVD) before the iteration. A numerical simulation and a measurement example is verified the effectiveness of the proposed method, which show a comprise between accuracy and efficiency.

Hexagonal ground-shielding through silicon vias (TSVs) in 3D ICs are explored based on measurement and simulation. The measured S-parameters of the TSV-bundle part are successfully extracted by de-embedding technique. The results math well with simulations up to 20GHz. The proposed TSV bundle has a good performance of return and insertion loss. For the hexagonal ground TSV shield system, the crosstalk analysis of neighbor signals in the TSV shield system is made based on the measurements and simulations. The electronic and magnetic field plots show a good capacitive and inductive coupling isolation for the victim signal TSV with shielding ground TSVs. Compared to those coupled-TSVs systems without ground guide, the ground-shielding TSV as well as coaxial TSV has higher noise over the range of frequencies.

To provide a guideline for converter design and fault protection, the failure mechanism and reliability of silicon carbide (SiC) power MOSFETs needs to be further investigated. In this paper, the failure mechanism during short-circuit (SC) of commercial 1.2-KV/19-A SiC power MOSFETs was investigated. After the SC tests, the I ds of the device decreased significantly. Moreover, it was found that the V th and I gs increased obviously. The results demonstrated that negative charges were captured by the gate oxide and accumulated during the SC tests, which is eventually causes degradation of the gate oxide. The results of this study may be useful in the design and application of SiC power MOSFETs.

With the development of avionics system, the demand of health metrics of integrated system is getting stronger and stronger. By describing the requirements and resources of an integrated system logically, a requirementoriented health metrics method of integrated system is proposed in this paper, then a reconstruction model of system resources is proposed depend upon the method. Furthermore, the decision-making method based on health metrics of integrated system is discussed.

Only bulk diffusion occurs in the solder joint of the monocrystalline structure without grain boundary diffusion. The migration direction of intermetallic compounds (IMCs) is mainly determined by grain orientation. Correspondingly, both bulk diffusion and grain boundary diffusion exist in the polycrystalline structure solder joints. The grain boundaries with random orientation and different lengths are distributed in the bumps, which can effectively inhibit the IMCs migration under the stressing of electron flow. The structure of lead-free solders mainly composed of Sn-based solder tends to nucleate cyclic twin structure with only two grains. The misorientation angle between the two grains is calculated to be a constant value of 57.2 degrees in this study. It is confirmed that the solder joints of the cyclic twin structure have a excellent inhibitory effect on electromigration failure.

The decay length scaling behavior of state-to-state coupling between silicon valence band $(VBMsi)$ and oxygen vacancy defect $(E_{defect})$ in Si/SiO2 interface is thoroughly investigated by density-functional theory. The detailed coupling process is revealed, and the scaling rate with interface-defect distance is obtained. Results show that the coupling constants $(Vc)$ decay with the defect distance is not so fast as the WKB approximation predicts, and the reason lies in the fact that the tunneling picture overestimates the localization of the defect states.

To deeply understand the charge trapping process in high-k gate stacks, we theoretically investigate the hole trapping characteristics of interfacial oxygen vacancies in (110) and (100) Si/SiO 2 /HfO 2 stacks. Si/SiO 2 and SiO 2 /HfO 2 interfacial defects are studied, and the hole trapping rate of each defect is calculated through ab initio simulation combining density-functional theory and Marcus theory. Among the possible hole traps considered in this work, it is suggested that the oxygen vacancies at SiO 2 /HfO 2 interface are the dominant under strong negative gate bias stress, and those at Si/SiO 2 interface can be effective traps only when hydrogen atom (H) or hydroxyl (OH) is induced at the vacancy. Moreover, the most dominant hole trap among the considered traps in the (110) structure locates at the Si/SiO 2 interface, while that in the (100) structure locates at the SiO 2 /HfO 2 interface.

This paper presents a novel VSWR measurement system for high power electronic vacuum device such as traveling wave tube in working mode. The measurement principles of this VSWR measurement system have been presents. The feasibility of this VSWR measurement system has been analyzed.

Field Programmable Gate Array (FPGA) system is widely used in deep learning application and cloud system for acceleration. Quality and reliability of IP block is essential to the successful development of today's complex hardware acceleration design. In this paper, we discuss the important issues of quality and reliability of digital soft IP, and propose a qualification measurement system that can evaluate IP quality. The metric system consists of eight categories to characterize IP quality. Based on this indicator system, we propose an IP qualification frameworks. As a case study, the proposed framework has been used to qualify three open source IP cores. The experimental results show that the proposed metric system and qualification framework can not only quantify the quality of IP, but also speed up the certification process and improve the accuracy of the certification results.

As we known, the measurement of junction-to-case thermal resistance (R th -JC) of semiconductor power devices is very important. In this paper, an approach of transient dual interface method (TDIM) with gate-source voltage (Vg s ) as the temperature sensitive electrical parameters (TSEP) was investigated for the measurement of R th -JC of packaged SiC MOSFET. The measured R th -JC value of packaged SiC MOSFET is in the range of 1.61 K/W to 1.76 K/W, and compared with the typical value of device specification, the maximum error is 5.29 %. The results show that the thermal resistance measurement of packaged SiC MOSFET by TDIM with Vg s as the TSEP is feasible, and it is of good accuracy and reproducibility.

Single-event performance of 65 nm CMOS SRAM technology was revealed by Monte-Carlo methods, with heavy ions energy ranging from 20 MeV/n to 2 GeV/n. By comparing the energy-deposition spectrums in sensitive volumes (SV) and single event upset (SEU) cross sections, it was found that secondary electrons and nuclear reactions of the 200 MeV/n incident ions have significant impact on the device response. Secondary electrons excited by the energetic space ions can spread beyond the SV of the 65 nm bulk CMOS SRAM and result into partial collection of the ion track. This mechanism causes the constant increase of SEU cross section with ion LET, even deviating from the surface area of the SV by 3.3×. Nuclear reaction can lead to unexpectedly large energy-deposition events in the SV by 10x than the initial LET, which create SEU cross sections in the sub-LET th region, although with lower probability than direct-ionization process by 104×∼105×. Higher ion energy seems to enhance the influence of secondary electrons and nuclear reaction. Moreover, soft error rates of the 65 nm bulk CMOS SRAM technology on GEO were predicted and discussed.

Single event effects (SEE) in two commercial-off-the-shelf (COTS) Ferroelectric Random Access Memory (FeRAM) technologies were investigated by heavy ions and pulsed laser irradiation. At least six SEE types were observed. The majority of the errors were caused by anomalies in the peripheral circuit, which was confirmed by the mirror SRAM technique, non-volatile test mode, and the detailed error information. Single event upset, single event functional interrupt and single event latchup cross sections were reported, with weak dependence on the supply voltage.

Hardware Trojan embedded by adversaries has emerged as a serious security threat. Until now, there is no a universal method for effective and accurate detection. Since traditional analysis approaches sometime seem helpless when the Trojan area is extremely tiny, this paper will focus on the novel detection method based on frequency spectrum analysis. Meanwhile, a failure physics model is presented and depicted in detail. A digital CORDIC IP core is adopted as a golden circuit, while a counter is utilized as a Trojan circuit. The automatic test platform is set up with Xilinx FPGA, LabVIEW software, and high precision oscilloscope. The power trace of the core power supply in FPGA is monitored and saved for frequency spectrum analysis. Experimental results in time domain and frequency domain both accord with those of theoretical analysis, which verifies that the proposed failure physics model is accurate. In addition, due to immunity to vast measurement noise, the novel method processing in frequency domain is superior to the traditional method conducting in time domain. It can easily achieve about 0.1% Trojan detection sensitivity, which indicates that the novel detection method is effective.

Electromagnetic interference effects in the bipolar voltage comparator was investigated in this paper. By using of bulk current injection (BCI), the coupling current stimulated by high power electromagnetic pulse was simulated. The experimental results shown that the aberrations such as pulse deriving and pulse width altering will come into being in the output waveforms of LM139 after current injection respectively. Furthermore, the coupling effect of pulse deriving and pulse width broadening were observed simultaneously in the higher level current injections.

Single event transient effect in the linear voltage comparator is investigated in this paper. The circuit level simulation is performed to analyze the output response of LM139 voltage comparators with single event transients (SETs). Simulation results show that input stage and two current sources are the most sensitive parts to the single event transient effects. The output responses were shown as transient pulses with different width. Based on the simulation results, the susceptive parts of a LM139 voltage comparator are acquired. Furthermore, the results above can also be helpful to further harden designs of linear ICs.

Malicious modification of integrated circuits referred to as Hardware Trojan fabricated in untrusted foundries pose a growing concern on reliable and security application. In order to ensure trusted in-filed operation of integrated circuits, many techniques are developed to authenticate Hardware Trojan often called trojan detection. Among these techniques side-channel signals analysis is a widely researched method to detect Hardware Trojan but suffer from sensitivity decreasing caused by increasing process variation effects. In this paper, we propose a non-invasive Hardware Trojan detection method which is immune to process variation effects. The method exploits the intrinsic relationship between transient current (I ddt ) and quiescent current (I ddq ) and I DDT of different test vectors that can eliminate the effects of process variation. The proposed method is verified by Hspice simulation carried on ISCAS 85 benchmark circuit. The 100 times simulation results with 130nm CMOS process using Monte Carlo method show that the suggested methods are capable of detecting the Hardware Trojan whose equivalent area is as small as 10"4 of the total size of the circuit in the presence of ±7% parameter(threshold voltage) variations.

Modern science is pushing Integrated circuits (IC) to higher level of integration, internal clock frequency and translation rates. In this context, the electromagnetic compatibility (EMC) of IC has gained more and more significance in the design stage, as well as the qualification. In this paper, the near field characterization is performed on a newly-built scanning system, in which a spectrum analyzer is used to detect the electromagnetic signal of the device under test. The scanning and detecting for the electromagnetic interference (EMI) is verified by a testing on the magnetic field above a microstrip. And then we apply the method to near field characterization of EMI for a microcontroller (C8051F120). The microcontroller is set to work at two different frequencies, 24.5MHz and 98MHz. The harmonic frequency is found in the range up to 500MHz. It is found that the excitation of phase lock loop module is significant for the whole electromagnetic radiation. The pins with higher EMI radiation are also identified in this paper.

Malicious modification of integrated circuits, namely Hardware Trojan, has emerged as a major security threat. Since it is extremely difficult to detect the presence of such small Trojan circuits using only logic test or side-channel analysis, this paper presents a novel test method combining logic test and side-channel test together. An 18-bit CORDIC IP core is adopted as a golden circuit, while a 2-bit counter is applied as a Trojan circuit. The automatic test platform is set up with Xilinx FPGA, LabVIEW software, and high precision oscilloscope. Meanwhile, the power traces of power supplies V ccint or V ccaux in FPGA are both monitored to enhance the detection sensitivity. The relevant test flow chart is also depicted in detail. Experimental results demonstrate that the novel test method can easily achieve about 0.1% Trojan detection sensitivity when principal component analysis approach is adopted as the data processing algorithm.

Total ionizing dose (TID) radiation effects in the bipolar voltage comparator with different biases and dose rates were investigated in this paper. The experimental results show that offset voltages shift after irradiation. Dominated by the current gain degradation of differential PNP transistors, the shifts of offset voltage and output characteristics were significantly affected by biases at high dose rate. Dominated by the current gain degradation of NPN transistors, the shifts of offset voltage and output characteristics were similar in all biases at low dose rate.

This paper proposed a two-dimensional thermal impedance model for amorphous silicon thin film transistors (a-Si:H TFTs) from a system of coupled energy equations, heat flowing equations and boundary conditions. By using of this model, the channel temperature distribution and thus the maximum channel temperature can be calculated. This model can be applied to describe the thermal behavior and thermal reliability of a-Si:H TFTS in the design phase.

The effect of Pb content in the rang of 0∼37wt.% on solidification behavior and shear performance of Sn3.0Ag0.5Cu/Cu joint was investigated. It was shown that Pb contamination showed a significant influence on the solidification behavior of Sn3.0Ag0.5Cu/Cu joint. A little amount of Pb resulted in the formation of ternary eutectic Sn-Pb-Ag phase with a low melting temperature and a mushy region between primary solidification phase and Sn-Pb-Ag phase during solidification stage of mixed joint. The mushy zone decreased with the increasing of Pb content and disappeared when Pb content in solder matrix of joint exceeded 18.34wt.% The addition of Pb in Sn3.0Ag0.5Cu/Cu joint has been shown to be beneficial to improve the shear force of SAC/Cu joint by using ball shear test method and the shear force of single interface mixed solder joint was in parabolic relationship with Pb content. The formation of ternary eutectic Sn-Pb-Ag phase and mushy zone in solidification stage had no obvious influence on the shear force of mixed solder joint.

Firstly, the storage failure mode and failure mechanism study of the klystron was carried out, the main failure modes of klystron in storage were summarized, and the failure mechanism and failure reasons of the main failure mode were analyzed. The results of the study showed that the vacuum degree decline is the main reason for the failure in long-term storage of klystron. The vacuum degree decline of tube is due to the residual gas of in seal manufacturing process or the deflation and shell leakage of the tube during the period of storage. Secondly, the generation process of residual gas was studied. At last, a failure sample of long-term storage klystron was analyzed; results showed that the failure mechanism was due to a large number of evaporation the cathode emission material which induced the serious degeneration of cathode, then the cathode emission current reduced and the out power declined. The reason of cathode degradation was vacuum degree decline in long-term storage process, ions back to the cathode surface that caused the huge evaporation of cathode emitting material.

When the Minimum channel length shrink to 0.13μιη, As the device geometry size scaling down while the operation voltage of the device decreased, but the electric field increase. The current density is still high in interconnect line, various failure mechanisms still exist in the process generation of copper interconnect/low k dielectric integrated, the reliability is still a very important problem. By using accelerated test, the reliability of the main failure mechanisms have been evaluated, the results showed that the lifetimes of main failure mechanism can achieve the requirements of more than 10 years lifetime. In the same time, NBTI effect will become the main failure mechanism in ultra deep sub-micron CMOS process when Minimum channel length becomes less than 0.13 μιη.

Experimental evidences are presented showing the variety of supply voltage dependence of single event upset (SEU) sensitivity in diverse SRAM devices. Devices under test (DUTs) from Alliance Memory, ISSI and IDT companies with different technologies were irradiated by several kinds of heavy ions at Heavy ion Research Facility in Lanzhou (HIRFL) cyclotrons. For the Alliance 256 kb SRAM device, SEU cross section increases by more than one order of magnitude as supply voltage decreases from 5.0 V to 3.0 V. SEU data of Alliance 64 kb SRAM also exhibits significant supply voltage dependence. The reduction of critical charge is the predominant factor worsening the device performance. While for the Alliance 8 Mb, ISSI 2 Mb and IDT 256 kb SRAM devices, no obvious trend was observed, which is attributed to the negligible net contribution of competing mechanisms. Those results suggest that the worst-case supply voltage for evaluation of SEU sensitivity depends on the test devices.

We have submitted the AlGaN/GaN High electron mobility transistors (HEMTs) to the high temperature reverse bias(HTRB) stress to assess their reliability for high voltage operations. The effects of HTRB stress as a function of the V DG and stress time on the DC parameters and trapping effects were investigated. The study was based on combined DC and pulsed characterization, transient measurement. It provides the following information: 1) the exposure to HTRB may result in a permanent degradation in on-state current, the transconductance, and a slightly positive shift of threshold voltage; 2) the high temperature (T A =175°C) step reverse bias (V DG stepped from 20V to 80V) stress tests revealed that the gate leakage current I GS increased abruptly after 50V stress voltage V DG ; 3) interestingly, the long term high temperature moderate reverse bias(V DG 40V) stress resulted in some positive effects such as the decrease of gate leakage current, improved gate lag characteristics and the decrease of current collapse in pulsed measurement during the whole test; 4) the reverse-bias voltage is the key factor but for reliability assessment of AlGaN/GaN HEMTs for high voltage application based on HTRB stress; 5) The degradation mechanism of the gate leakage current under relatively high voltage HTRB test has been ascribed to the degradation metal and semiconductor interface; 6) the improved I-V characteristic under moderately voltage HTRB test has been attributed to the reduction of lateral tunneling current.

This paper presents an equivalent circuit approach to evaluate the effect of near-zone electromagnetic interference on the shielding effectiveness (SE) of an apertured rectangular enclosure. The approach is an extension of Robinson's equivalent circuit formulation. The extension in this paper is carried out by using an electric dipole to represent the external interference and applying the electric field at the aperture caused by the dipole to replace Robinson's incident plane wave. The SE correlates to the dimensions of the enclosure and the aperture. The distance from the interference to the enclosure and the observed position within the enclosure are significant parameters on the SE evaluation. The shapes of the aperture also affect the SE. This equivalent circuit approach based on the available analytical formulation provides a fast means of investigating the effect of design parameters on the SE of an apertured enclosure for near-zone interference and can be used for designers of shielded enclosures.

This paper presents a novel optimization design method for the closed loop control of the sense mode of a MEMS gyroscope, which aims at improving the performances and reliability of the control system.

Along with the infrared technical rapid development, infrared radiation (IR) thermal imaging technology is widely applied in device and circuit reliability research. For device and circuit reliability study, IR thermal imaging technology is best for getting the peak temperature and temperature distribution. With the peak temperature and temperature distribution, the thermal information of the devices were evaluated and optimized to meet the design requirement. Secondly, IR thermal imaging technology is used to position hotspot for failures analysis, example for especially increases in elevated leakage currents. However, IR thermal imaging technology can provide evidence of excessive temperature rise due to power dissipation. It can identify root-cause of failures at temperatures below expectations.

Space traveling wave tube (TWT) is one kind of microwave vacuum tube for communication, which must have high reliability, high power. The life of the space TWT is requested for a long lifetime of 10–15 years. In order to shorten the testing process, accelerated aging tests are performed at higher than normal operating temperature and currents of cathode. But in the process of the actual test, the cathode degradation is very slow, the test time is too long for all samples failing to get the lifetime data. In order to obtain the lifetime of the long life tube in a short time, it is necessary to investigate a new method which can evaluate the long lifetime through short-term working data. This paper introduced how to solve the zero-failure test data with small samples. With no failure data in data processing of life test, parameter degradation extrapolation method is used to obtain the failure life time. All the expected life of the sample was estimated of each test samples by least-square method for linear fitting and the goodness of fit and the significance testing was done.

This work aims to characterize the microstructure and temperature field of the hermetic packaging structure by welding the cover made of Kovar alloy and the base made of a low-carbon low-alloy steel (i.e., #10 steel) using parallel seam welding (PSW) process. The microstructure of welded joints and distribution of elements were analyzed by scanning electron microscopy (SEM) equipped with energy dispersive spectrometer (EDS). Welding mechanism of PSW is discussed and temperature field of PSW is studied by a nonlinear transient finite element analysis. In FEM simulation, the surface contact pair is created to form weld beam and the heat generated by a pulse current is taken as a moving heat source. The results show that the maximum temperature in the weldment is 1105.3 °C, which is below the melting point of Kovar alloy and #10 steel (both in 1400∼1500°C). The cross-sectional microstructure analysis results of the welded joint show that welded junction is localized between the plating layers of two base materials, both Kovar alloy and #10 steel did not melt during the welding process. Numerical simulation value of the temperature at the plating coat layer on Kovar side is larger than that on #10 steel because of boundary conditions and thermal conductivity. Same phenomenon can be seen at the location 3 mm away from the weldment. The temperature on the node of Kovar with a distance of 5 mm from the weldment is 796 °C.

Electromigration has a potential to be used as a process for microstructural design in ultrafine interconnects such as TSVs and microbumps. This study investigates the relationship between the electromigration and the microstructural evolution in a Cu/Sn-microbump/Cu structures through a modeling and simulation approach. The electromigration-induced polarity effect on the interfacial Cu6Sn5 and Cu3Sn compounds as well as the acceleration of the Cu pad consumption are found, as previously reported in experimental studies. In addition, the simulation results predict that the Cu6Sn5 grains at the anode become finer when an current is applied. The polarity effect is weaker when the pad size increases from 10 μm to 20 μm. In the larger microbump, the growth of the interfacial Cu6Sn5 is slower, while the growth of the interfacial Cu3Sn and the consumption of the Cu pad is faster. The growth of the interfacial IMCs and the consumption of the Cu pad at both electrodes are faster in the hourglass-shaped microbump. The interfacial Cu6Sn5 layer at the anode in the barrel-shaped microbumps appears to be convex, while concave in the hourglass-shaped microbump. The polarity effect becomes more pronounced when bulk Cu6Sn5 grains in the Sn microbump are dissolved and redeposited onto the interfacial Cu6Sn5 at the anode. The bulk Cu6Sn5 grains are predicted to migrate towards the anode driven by the electric current.

Inherent reliability of Surface acoustic wave filters plays a key role for its application in the mobile communication systems. Construction analysis is an effective method for evaluating the inherent reliability of electronic components. This work provides a construction analysis process for the surface acoustic wave filters, which includes external encapsulation analysis, internal encapsulation analysis and chip-level analysis. The results show that oxidation occurs on the upper surface of the Al electrodes and leads to the formation of Al2O3. The break in the Al electrode stripe is observed.

Total Dose ionizing radiation response of substrate PNP transistors have been investigated as functions of biases and dose rates. The experiment result shown that emitter-base junction bias dominates dose rate effects in the SPNP transistors. By considering of radiation induced interface traps and oxide trapped positive charges, the degradation mechanisms have been discussed based on space charge model. In addition, the worst case biases in the SPNP transistor with different dose rates are also discussed in this paper.

This paper proposed a physical model for reverse subthreshold currents in the amorphous silicon thin film transistors. Firstly, an approximation for the band bending in the back interface as a function of gate-source voltage is derived. By considering of deep states, a current model based on electron conduction in the back channel is then developed. Finally, the proposed model was verified using the experimental data.

The failure rate for NMOS devices is modelled by sum-of-failure-rate, i.e., the one for HCI mechanism and the one for TDDB failure mechanism. The least squares method is used to estimate the unknown parameters in HCI failure rate model and TDDB failure rate model, respectively. The hypothesis tests show that the regression model for HCI (TDDB) has good fitness and high significance. These results are verified by a numerical example.

A prognostic circuit for electromigration failure of integrated circuit was proposed, and it was simulated on the base of the SMIC 0.18 um mixed-signal CMOS process model. The prognostic circuit is composed of stress and detection module, two-stage comparator, offset voltage cancellation module, non-overlapping clock generation module, and output module. When the increase amount of resistance for interconnect line exceeds a preset value due to electromigration, the output of the prognostic circuit designed to fail faster will jump from low voltage to high voltage. It indicates the impending failure of hosted circuit because of that the prognostic circuit experiences the same manufacturing process and operational environment as the hosted circuit. The research results are useful for the prediction of performance degradation and failure of integrated circuit.

This paper investigates the total dose effects of substrate PNP transistors through experiments. By considering of oxide trapped positive charges and interface traps, the radiation induced excess base current in the irradiated SPNP is simulated. The simulation results showed similar trends with the experimental results, thus the mechanisms of total dose effects in the SPNP transistors are verified.

Traveling wave tube (TWT) is a type of microwave vacuum electronic component. TWT often works under harsh mechanical environment stress, such as vibration, shock. The stress leads to the open circuit of filament in heater, which results in the change of inner structure and electric performances, even failure. This paper introduced a failure case of TWT in use. Failure mode and failure mechanism of filament in heater of a typical TWT was analyzed in this paper.

Ionization radiation causes ESD protection structure of integrated circuit degradation. A new method using Transmission Line Pulse (TLP) test is introduced in this article; this method gives more detailed information of the ESD protection structure's degradation. Turn-on voltage, hold voltage, turn-on resistance of two type ESD protection structures are measured before and after TID radiation test, results are discussed.

An investigation of thermal effects in a high power 3-5μm solid state laser pumped with different pump beam transverse profiles is carried out by COMSOL software based on the finite element method, and the temperature of the crystal center where the Super-Gaussian distributed light projected area is 81.8°C, and is bigger than that of Gaussian pump light mode and top plane pump light mode.

The electromagnetic interference effects in the μA741 operational amplifier circuit were investigated in this paper. Through the using of pulse injection, the output characteristics of μA741 were simulated by considering of EMI effects. Through sensitivity and smoke analysis, the simulation results shown that the differential input stage and the intermediate amplifying stage are the most sensitive and vulnerable function model in the μA741 circuits to EMI effects.

How to predict the end of discharge time for Li-ion battery is one of the most important problems in the field of battery health management. This paper proposes a linear regression model to describe the relationship between the end of discharge time and discharge cycle. Moreover, the model verification shows that the discharge cycle has significant effect on the end of discharge time and that the proposed model has good fitness in fitting Li-ion discharge data. This paper also presents the end of discharge time predictions for Li-ion battery based on the linear regression model.

Prognostics and health management has become a preferred approach to achieve warning or respond to impending failure of electronic systems. A prognostic circuit for hot carrier injection (HCI) failure of integrated circuit was proposed in the paper, and it was simulated on the base of the SMIC 0.18 um mixed-signal CMOS process model. The prognostic circuit consists of stress voltage generation module, HCI failure detecting module, two-stage comparator, offset voltage cancellation module, non-overlapping clock generation module, and output module. When the increase amount of threshold voltage for the MOSFET exceeds a preset value due to hot carrier injection, the output of the prognostic circuit designed to fail faster will jump from low voltage to high voltage. It indicates the impending failure of hosted circuit because of that the prognostic circuit experiences the same manufacturing process and operational environment as the hosted circuit. The research results are useful for the prediction of HCI degradation and failure of integrated circuit.

Total dose dependence of bias current and offset voltage in the linear operational amplifier μA741 with different bias is presented in this paper. The experimental results show that the bias current in the μA741 with grounded bias is significantly affected by the degradation of the differential input transistors. In addition, the offset voltage is affected by the degradation of bipolar transistors of the current source in the differential input stage.

In this paper, effect of bias dependence of substrate NPN (SNPN) transistors on total dose radiation is investigated. By considering of bulk field and fringing electric field in the oxide, the degradation mechanisms are discussed in numerical simulations. Experimental results show that the applied emitter voltage and the emitter-base junction bias play important roles in the total dose irradiation effect of SNPN transistors, which is agreement with the theoretical analysis.