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This letter proposes a new architecture of a simple and sub-1μs fast-response voltage-mode buck converter using adaptive on-time and frequency-locked controlled techniques. The adaptive on-time-controller with frequency-locked loop is employed to keep the switching frequency (fsw) constant at 1 MHz to achieve fixed frequency. Therefore, the switching losses, and frequency variations can be reduced to improve the converter efficiency. In addition, the proposed buck converter does not include slope compensation circuit, which will simplify the system design and shorten the transient response of the converter without adding extra acceleration circuits. Moreover, the transient response of the converter can be accelerated by choosing the appropriate equivalent-series-resistance (ESR) value for the load capacitance. The chip is fabricated in TSMC 0.35 μm 2P4M process. The experimental results show that the maximum efficiency is 90.04% when the load current is 140 mA and output voltage is 1.8 V. The load transient response time is about 0.96 and 0.94 μs when the load current changes from 100 to 500 mA and from 500 to 100 mA, respectively. [ABSTRACT FROM AUTHOR]

A new fast-response current-mode buck converter with improved $I^{2}$ -controlled techniques is presented in this paper. First, the proposed converter uses the improved $I^{2}$ -controlled techniques to design a new current-mode buck converter. The current-sensing circuit can fully sense the inductor current. The sensing current is divided into two paths; one is flown through the dynamic-acceleration circuit, and the other is transferred to hysteretic comparator to compare with dynamic-acceleration output. The $I^{2}$ -controlled techniques increase the bandwidth of the converter’s closed-loop gain that will speed up the converter’s transient response. Second, the converter uses the phase–frequency-controlled techniques to lock the switching frequency of the adaptive on-time generator of the proposed converter and reduce the difficulty of the output filter. Third, the circuit does not need slope compensation, so that it is very simple to implement. Fourth, the proposed buck converter was implemented with TSMC 0.35- $\mu \text{m}$ CMOS 2P4M processes, which is a low-cost process. The experimental results show that the maximum load current can be up to 600 mA, the input voltage range is 2.6–4 V, the output voltage is regulated at 1.8 V, the maximum power efficiency is up to 90%, and the transient response times are 2.5 and $2.8~\mu \text{s}$ at rising and falling edges, respectively. [ABSTRACT FROM AUTHOR]

A sub-1-μs ultrafast-response buck converter utilizing improved analog-voltage-dynamic-estimation (AVDE) techniques is proposed in this letter to improve previous works. First, the improved AVDE controller uses a new pseudocurrent circuit and a new ramp generator to get low gain, wide bandwidth, wide dynamic range, and low equivalent series resistor $(R_{{\text{ESR}}})$. Second, the proposed converter has high performance, fast transient response, and low output voltage ripple. Third, the circuit does not need slope compensation so that it is very simple to implement. The switching frequency of the proposed buck converter is 1 MHz for nominal 3.3-V input and 0.8–2.5-V output range application. The experimental results prove that the proposed scheme improves the transient response within 1.2 μs and its maximum power efficiency can be up to 91.9%. The fastest transient time of the proposed converter is only 0.8 μs as the switching frequency is equal to 1 MHz. The settling time of the proposed converter is only within 0.8 cycle of the switching frequency. The maximum load current is 300 mA. The proposed buck converter has been fabricated with a commercial 0.35-μm CMOS 2P4M process, and the total chip area is about {1.46 \;\text{mm}\times 1.5} mm, including PADs. [ABSTRACT FROM PUBLISHER]

This paper presents a new buck converter with optimum-damping and dynamic-slope compensation techniques. The optimum-damping control is a well-known current control method, and the proposed dynamic-slope generator can achieve frequency compensation to prevent subharmonic oscillation. When the system is disturbed, the proposed dynamic-slope generator can stabilize the circuit in a single cycle. Hence, the dynamic-slope compensation can be used to replace traditional extra slope compensation in the optimum-damping-control circuit. The measured transient time of the load current is 2 μs from 50 to 500 mA, and 3 μs from 500 to 50 mA. The optimum-damping-control techniques can rapidly reach desired output voltage in 2–3 switching cycles. The experimental and simulation results confirm that the proposed approach can achieve the slope compensation and accelerate the transient response. The proposed converter has been fabricated with TSMC 0.18 μm CMOS 1P6M technology. The converter's operating frequency is 1 MHz, the maximum output current is 500 mA, and the peak power efficiency is 89.68% under 300-mA load current. The chip area is only 1.0376 mm × 1.0599 mm (include PADs). [ABSTRACT FROM PUBLISHER]

This paper presents a fast-transient boost converter with noise-reduction techniques for wireless sensor networks. The modulator can be directly inputted by 0.8–1.2 V for 1.8 V output. The proposed low electromagnetic interference (EMI) boost converter is based on a fast delta–sigma controller. This paper proposes a fast delta–sigma modulator for a boost converter to solve the EMI problem. The proposed converter complies with Federal Communication Commission class B conducted emission limits, in which the harmonic level must be lower than −48 dB \mu \textV for frequency from 0.45 to 30 MHz. The measured results show that the maximum efficiency of the proposed converter is 90%, and the recovery time is 4 \mu \texts from heavy to light load and 8 \mu \texts from light to heavy load. The chip was fabricated in Taiwan Semiconductor Manufacturing Co., Ltd. 1P6M 0.18- \mu \textm complementary metal–oxide–semiconductor process, and the chip area is \sim 0.85 mm2. It is designed to operate from 1 to 2 MHz with a 3.3- \mu \text{H} inductor and a 10- \mu \text{F}$ output capacitor. The proposed converter output spectrum is lower than −70 dBm or −40 dB \mu \textV . [ABSTRACT FROM PUBLISHER]

This paper presents a low electromagnetic interference buck converter for wireless sensor networks with the spur-reduction techniques. The proposed buck converter uses the third-order delta–sigma modulator (DSM) with its noise-shaping characteristic to achieve low output noise. The DSM is designed with the chopper-stabilization techniques, which further reduces the impacts of low-frequency noises, such as flicker noise and offset voltage. The proposed buck converter also adopts fast transient path in order to get a fast transient response. The proposed buck converter has been fabricated with a TSMC 0.35- \mu \textm CMOS 2P4M process. The area of the whole chip is 2.18 mm2. Compared with previous works, the noise floor of the proposed converter’s output is below −76 dBm, which is lower than others. The settling time of the proposed converter’s output is \sim 20~\mu \texts with the load current skipping between 50 and 500 mA, that is faster than previous works, too. Moreover, the peak efficiency of the proposed converter is better and equals to 90%. [ABSTRACT FROM PUBLISHER]