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Introduction: Reconfigurable field effect transistors (RFET) have the ability to toggle polarity between n- and pconductance at runtime [1], [2]. The here presented multiple independent gate (MIG) RFET expands the device functionality by offering additional logical inputs, valuable for e.g. efficient XOR or majority gate implementations [3], [4] or the here originally presented multiplexer circuit. Moreover, for the first time with a top-down RFET approach equal ON-currents are obtained for every configuration while requiring only one supply voltage (VDD). Working principle: The presented RFET consists of an intrinsic silicon nanowire channel (Fig. 1a). At both ends NiSi₂ is intruded, which has a work function aligned near to the middle of the Si band gap. Each of the resulting Schottky junctions is gated individually (CG1, PG) and additional gates are introduced along the channel (CG2, CG3). The program gate (PG) determines the device’s polarity and has the same potential as the corresponding drain (0 V for hole or VDD for electron conductance). If all control gates (CG1-3) are biased equally, the RFET turns ON Fig. 3a, b, f, g). Whenever any or all CGs are biased equally to the source’s potential, a potential barrier is formed, switching the RFET OFF (Fig. 3c-e, h-j). Hence, the FET works as wired-AND logic gate (Fig. 6a). The fabrication with CMOS compatible processes and materials is based on a 20 nm silicon-on-insulator (SOI) wafer and requires no doping. The nanowire is formed by a reactive ion etch process [5]. By repeated oxidation and HF etching the wire is further rounded and thinned to ca. 60 nm width and 4 nm height. An omega-shaped gate stack of 5 nm SiO₂, and conductive TiN, Ti and Pt surrounds and radially compresses the wire (Fig. 1b). Finally, nickel is deposited at both ends of the wire and atomically abrupt and flat NiSi₂ Schottky junctions are formed (Fig. 1c). Performance: The transfer characteristics in Fig. 4 reveal an ON/OFF ratio of five orders of magnitudes and ONcurrents which are equal regardless of the programmed configuration. Additionally, only one supply voltage is needed for gates and drain. Despite its necessity for the use in complementary logic circuits, this symmetry was never achieved before for top-down fabricated RFETs. For NiSi₂ and Si, the Schottky barrier height is slightly lower for holes than for electrons leading to initially asymmetric ON-currents. However, by the influence of the omega gate stressor on the band structure the electron and hole injection through the Schottky barrier can be equalized as demonstrated in Fig. 2 [6]. Fig. 4 further shows that the minimum subthreshold swing SS and threshold voltage are lower for the switching with CG2 and CG3 than for all combinations including CG1. This is because CG1 directly controls the inlet at the Schottky junction whereas the other gates only build a conventional channel barrier. Having two efficiently switching gates (CG2+3), as demonstrated for the first time, thus improves the efficiency of RFETs. From Fig. 5 it can be seen that the gates’ voltage determines the shape of the output characteristics. Hole dominated currents rise with retard because the injecting Schottky barrier is still non-transparent for tunneling at VD = 0 V. Applications of the device reach from camouflage circuits for hardware secure authentication [7] and fine-grained FPGAs [8] over area and power-delay optimized circuits [3], [4] to novel logic synthesis based on majority-inverter graphs [9]. As a graspable and novel example, the presented device can serve as transmission gate (Fig. 6b) in a multiplexer (MUX) (Fig. 6c, d), which requires program gates at both in- and output. An n-bit MUX can be reduced by every second stage, thus only (2^[n+1]− 2^i)/3 transmission gates are required, with i=1 for odd and i=2 for even numbers of n (with classical CMOS: 2^[n+1] − 2). For a 4-bit MUX this results in altogether 30% less transistors when considering also the select and program signal inverters and the reduced buffer needs (Fig. 6e). Eventually, more gates per transistor can further reduce the transistor count, e.g. for a 5-gate RFET in a 6-bit MUX by even 42%. [1] A. Heinzig et al., Nano Lett., vol. 12, no. 1, pp. 119–124, (2012). [2] M. D. Marchi et al., in Electron Devices Meeting (IEDM), 2012 IEEE International, pp. 8.4.1–8.4.4, (2012). [3] P.-E. Gaillardon et al., in Test Symposium (LATS), 2016 17th Latin-American, pp. 195–200, (2016). [4] J. Trommer et al., in 2016 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 169–174, (2016). [5] M. Simon et al., IEEE Trans. Nanotechnol., vol. 16, no. 5, pp. 812–819, (2017). [6] T. Baldauf et al., Solid-State Electron., vol. 128, pp. 148–154, (2017). [7] Y. Bi et al., in 2014 IEEE 23rd Asian Test Symposium, pp. 342–347, (2014). [8] P. E. Gaillardon et al., IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 10, pp. 2187–2197, (2015). [9] L. Amaru et al., Proc. IEEE, vol. 103, no. 11, pp. 2168–2195, (2015).

3D vertically stacked silicon nanowire (SiNW) field effect transistors (FET) with high density arrays (up to 7×20) of fully depleted and ultra-thin (15–30 nm) suspended channels were fabricated by a top-down CMOS compatible process on silicon on insulator (SOI). The channels can be wrapped by conformal high-κ gate dielectrics (HfO 2 ) and their conductivity can be excellently controlled either by a reference electrode or by three local gates; a backgate (BG) and two symmetrical Pt side-gates (SG) offering unique sensitivity tuning. Such 3D structure has been (3-Aminopropyl)-triethoxysilane (APTES) functionalized and biotynilated for pH and streptavidin (protein) sensing, respectively. An ultra-low concentration of 17 aM of streptavidin was measured, the lowest ever reported in literature. Extremely high quasi-exponential drain current responses (ΔI d /pH) of ∼0.70 dec/pH were measured for structures with APTES functionalized SiO 2 gate dielectrics when operated in the subthreshold regime. Also, high drain current responses > 20 µA/pH and high sensitivities (S ∼ 95%) were measured for structures with a native oxide gate dielectrics when operated in the strong-inversion regime.

A 3D, vertically stacked silicon nanowire (SiNW) field effect transistor (FET) featuring a high density array (7×20) of fully depleted channels has been successfully fabricated by a CMOS compatible process on silicon on insulator (SOI) and functionalized for streptavidin detection for the first time. The channels are surrounded by conformal high-κ gate dielectrics (HfO2), and their conductivity can be uniquely tuned by three gates; a backgate (BG) and two symmetrical Pt side gates (SG) through a liquid, offering unique sensitivity tuning with high gate coupling (SS=75 mV/dec, α'=SS60mV/dec/SSmeasured=0.8, with highest sensitivity=93-99%, obtained for I=1 0pA-10nA, in weak inversion) ever published.

An initial top-down process of Germanium nanowires is developed in this work. The Silicon Nitride (Si 3 N 4 ) is used as a hard mask to obtain a stable surface for lithography and a resistive mask for etch. The electron-beam lithography (EBL) is utilized for patterning the nanowires with Hydrogen Silsesquixane (HSQ) as a negative photoresist. Several different etch conditions are examined to transfer the patterns into the substrate.

A 3D, vertically stacked silicon nanowire (SiNW) field effect transistor (FET) featuring a high density array (7×20) of fully depleted channels has been successfully fabricated by a CMOS compatible process on silicon on insulator (SOI) and functionalized for streptavidin detection for the first time. The channels are surrounded by conformal high-κ gate dielectrics (HfO2), and their conductivity can be uniquely tuned by three gates; a backgate (BG) and two symmetrical Pt side gates (SG) through a liquid, offering unique sensitivity tuning with high gate coupling (SS=75 mV/dec, α'=SS60mV/dec/SSmeasured=0.8, with highest sensitivity=93-99%, obtained for I=1 0pA-10nA, in weak inversion) ever published. © 2013 IEEE.