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ESD robustness for self-protected advanced Silicon photonic components integrated into optical interposers is reported, including industry-first CDM data. HBM performance in reverse bias polarity is shown to be the limiting factor and is correlated to the optical component width. The Ge-EAM modulator with heater is found to be the weakest element CDM-wise.

Future high-performance applications require in-package optical modules to enable the high bandwidth requirements. This is enabled by the co-integration of a silicon photonics module with a host IC in a single package. Since the silicon photonic elements are very sensitive to temperature changes, the optical performance can be affected by the thermal coupling effects in these co-integrated packages.In this paper, a thermal modeling study is presented for the test case of a BGA package that contains a 300W host IC and an Si photonics optical I/O module with 32 channels. The thermal model, calibrated with global package level measurements, are well as with local device measurements, shows a large level of thermal coupling from the host IC to the optical module. Although the thermal coupling between individual photonic elements is shown to be in the order of 1%, the combined thermal coupling for the 32 channels reaches 28%, indicating the clear need for a detailed thermal analysis.

Carrier-depletion monolithic III-V/Si optical phase modulators are proposed and numerically investigated. Thanks to the larger carrier-induced refractive index change of the III-Vs compared to Si, the III-V/Si phase modulator is predicted to achieve 0.07-Vcm modulation efficiency at 16-dB/cm optical loss at 1310-nm wavelengths.

We demonstrate an O band 40Gb/s silicon microring modulator assembled with a 1V driver in a 52km metro transmission experiment without dispersion compensation, achieving a record high bandwidth distance product of 2080 Gbkm/s.

We demonstrate a 20Gbit/s single-layer graphene EAM based on p-doped graphene on p-doped waveguide with 4.4dB extinction ratio and >15.7GHz 3dB bandwidth at OV DC bias across 70nm wavelength range.

We demonstrate a microbump flip-chip integrated 14nm-FinFET CMOS-Silicon Photonics (SiPh) technology platform enabling ultra-low power Optical I/O transceivers with 1.6Tb/s/mm2 bandwidth density. The transmitter combines a differential FinFET driver with a Si ring modulator, enabling 40Gb/s NRZ optical modulation at 154fJ/bit dynamic power consumption in a 0.015mm2 footprint. The receiver combines a FinFET trans-impedance amplifier (TIA) with a Ge photodiode, enabling 40Gb/s NRZ photodetection with −10.3dBm sensitivity at 75fJ/bit power consumption, in a 0.01mm2 footprint. High-quality data transmission and reception is demonstrated in a loop-back experiment at 1330nm wavelength over standard single mode fiber (SMF) with 2dB link margin. Finally, a 4×40Gb/s, 0.1mm2 wavelength-division multiplexing (WDM) transmitter with integrated thermal control is demonstrated, enabling Optical I/O scaling substantially beyond 100Gb/s per fiber.

We present an accurate model for self-heating effect in depletion-type Si micro-ring modulator which describes incident-power dependent transmission and dynamics. Its accuracy is confirmed with measurement. It can be useful for determining optimal modulation conditions.

We present a new small-signal model for the modulation frequency response of a Si micro-ring modulator. The model is based on the coupled-mode theory and has the well-known second-order system characteristics. The accuracy of the model is confirmed with measured Si MRM small-signal frequency response.

We derive a small-signal model for modulation response of a Si ring modulator. Our model is based on the multiple round-trip model but it gives simple but accurate description of the ring modulator modulation dynamics.

The growing demand for I/O bandwidth in high-performance applications, such as datacenter switches and HPC nodes, drives the need for on-package integration of Optical I/O modules with the host CMOS ICs [1]. Silicon Photonics (SiPh) is a prime technology platform to realize multi-Tb/s hybrid CMOS-SiPh modules for $1\mathrm {m}-500\mathrm {m} +$ optical interconnect distances [2]. Such Optical I/O modules require interfaces for dense, high-speed electrical I/O and low-noise power and ground delivery, which can be enabled by the integration of through-silicon vias (TSV) into the SiPh platform. Here, we describe challenges and results for $10 \mu \mathrm{m} \times 100 \mu \mathrm {m}$ TSV-middle integration into a 300mm SiPh interposer platform. TSVs with low RF loss up to 50GHz are demonstrated along with low SiPh waveguide losses and high-performance Ge photodetectors.