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In order to reduce the pollution of electric vehicle charging modules to power grid and improve the disadvantages of low efficiency, low power and low system reliability, a multi-charging module design scheme based on average current method was proposed. The proposed module consists of three-phase VIENNA rectifying circuit with a high power factor and LLC resonant converter. The one cycle control strategy is adopted to realize the power factor correction of the front stage and reduce the pollution caused by harmonics. The control strategy of average current method is adopted between modules to ensure the same output current of each charging module. In this paper, the working principle and control strategy of each module are analyzed. At last, two 4KW experimental prototypes are developed, and the feasibility of the multi-charge module scheme designed in this paper is verified through experiments.

For the purpose of synchronization of three independent DC motors which were used to drive the supporting poles of a table-lift, a “master-servant” structured control scheme is introduced. By taking the master pole's output as reference signal and the servant pole's output as feedback signal, servant poles become the followers of the master pole. Hall sensors are employed to transmit the rotations of the motors as well as the upward or downward speeds of the supporting poles into pulse signals. These pulse signals are counted by a micro-processor and then processed numerically. Using a special counting method, the difference between the outputs of the master and servant poles creates an error signal. This way, the lengths of the registers for pulse counting are limited to 8 bits, no matter how many pulses reach the micro-processor. Two numerical arithmetic schemes for the pulse width modulation are used for even more precise control. Experimental results are also presented.

With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bank-interleaved distribution of the address space. Although such an organization is effective for avoiding access hot-spots, it can cause a significant number of non-local L2 accesses for many commonly occurring regular data access patterns. In this paper we develop a compile-time framework for data locality optimization via data layout transformation. Using a polyhedral model, the program's localizability is determined by analysis of its index set and array reference functions, followed by non-canonical data layout transformation to reduce non-local accesses for localizable computations. Simulation-based results on a 16-core 2D tiled CMP demonstrate the effectiveness of the approach. The developed program transformation technique is also useful in several other data layout transformation contexts.

The display of realistic ocean environment is one of the most important research fields in computer graphics. In this work we present a practical algorithm for real-time rendering of realistic and unbounded ocean. Relying on the newest features of graphics programmable units (GPU), our method adopts parallel computing technique for generating ocean surface in GPU and uses efficient shading trips for rendering optical effects of ocean surface. The main features of our work concentrate on three fields: ocean surface generation in CUDA (Compute Unified Device Architecture), adaptive ocean surface tessellation based on level-of-detail (LOD), and sophisticated optical effects. Experimental results show that our approach is effective and satisfies the requirements of a realistic real-time simulation system for unbounded ocean environment.

A novel filter is proposed by applying back propagation neural network (BPNN) ensemble where the noisy signal and the reference one are the same in a learning process. This neural network (NN) ensemble filter not only well reduces additive and multiplicative white noise inside signals, but also preserves signals' characteristics. It is proved that the reduction of noise using NN ensemble filter is better than the improved epsilon nonlinear filter and single NN filter while signal to noise ratio is smaller. The performance of the NN ensemble filter is demonstrated in computer simulations and actual electroencephalogram (EEG) signals processing.

Bioinformatics applications constitute an emerging data-intensive, high-performance computing (HPC) domain. While there is much research on algorithmic improvements, (2004), the actual performance of an application also depends on how well the program maps to the target hardware. This paper presents a performance study of two parallel bioinformatics applications HMMER (sequence alignment) and SVM-RFE (gene expression analysis), on Intel x86 based hyperthread-capable (2002) shared-memory multiprocessor systems. The performance characteristics varied according to the application and target hardware characteristics. For instance, HMMER is compute intensive and showed better scalability on a 3.0 GHz system versus a 2.2 GHz system. However, SVM-RFE is memory intensive and showed better absolute performance on the 2.2 GHz machine which has better memory bandwidth. The performance is also impacted by processor features, e.g. hyperthreading (HT) (2002) and prefetching. With HMMER we could obtain -75% of the performance with HT enabled with respect to doubling the number of CPUs. While load balancing optimizations can provide speedup of -30% for HMMER on a hyperthreading-enabled system, the load balancing has to adapt to the target number of processors and threads. SVM-RFE benefits differently from the same load-balancing and thread scheduling tuning. We conclude that compiler and runtime optimizations play an important role to achieve the best performance for a given bioinformatics algorithm.