86 results on '"Yoneda T"'
Search Results
2. Power-Constrained Test Scheduling for Multi-Clock Domain SoCs
3. Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories.
4. Improving Dependability and Performance of Fully Asynchronous On-chip Networks.
5. Plate wave resonator using rotated Y-cut single crystal LiTaO3 thin film made by ion implant technology.
6. Aging test strategy and adaptive test scheduling for SoC failure prediction.
7. A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs.
8. RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC.
9. Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing.
10. Seed Ordering and Selection for High Quality Delay Test.
11. Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs.
12. A circuit failure prediction mechanism (DART) for high field reliability.
13. N-way ring and square arbiters.
14. Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.
15. Partial Scan Approach for Secret Information Protection.
16. Delayed feedback altitude control for micro UAV without sensing pitch rate.
17. Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths.
18. Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects.
19. Asynchronous pipeline controller based on early acknowledgement protocol.
20. A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper).
21. TAM Design and Optimization for Transparency-Based SoC Test.
22. Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.
23. Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing.
24. Test Scheduling for Memory Cores with Built-In Self-Repair.
25. Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip.
26. Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints.
27. Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.
28. Symbolic Model Checking of Analog/Mixed-Signal Circuits.
29. Telemedicine system using 3 - D high definition image.
30. Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing.
31. Hazard Checking of Timed Asynchronous Circuits Revisited.
32. Power-Constrained SOC Test Schedules through Utilization of Functional Buses.
33. Fiber-optic thermometer application of Eu end doped silica fiber Sensor.
34. Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability.
35. A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.
36. High level synthesis of timed asynchronous circuits.
37. Synthesis of speed independent circuits based on decomposition.
38. An efficient scan tree design for test time reduction.
39. Multimedia and routing specific applications on IPv6 networks.
40. Verification of timed circuits with failure directed abstractions.
41. Design for consecutive transparency of cores in system-on-a-chip.
42. Area and time co-optimization for system-on-a-chip based on consecutive testability.
43. Level oriented formal model for asynchronous circuit verification and its efficient analysis method.
44. Small-sized resonator IF filter using shear horizontal wave on heavy metal film/quartz substrate.
45. A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification.
46. Partial order reduction in verification of wheel structured parameterized circuits.
47. Framework of timed trace theoretic verification revisited.
48. A DFT method for core-based systems-on-a-chip based on consecutive testability.
49. Conformance and mirroring for timed asynchronous circuits.
50. Reduction of the number of terminal assignments for detecting feature interactions in telecommunication services.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.