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Embedded memories have been used extensively in modern SoC designs. In order to estimate the power consumption of entire design correctly, the more accurate memory power model is needed. However, the memory power model which is commonly used in commercial EDA tools is too simple to estimate the power consumption accurately. In this work, we propose two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider the switching activity for both control and non-control signals thus can raise the accuracy of traditional memory power models. The proposed dummy modular approach links our enhanced memory power model to commercial power estimation flows. The experimental results have shown that our memory power model is more accurate than the traditional memory power model.

The discrete cosine transform (DCT) has been widely used as the core of digital image and video signal compression. In this paper, we present a high throughput 8/spl times/8 2D DCT/IDCT architecture which is well suited for the application in real time image or video system. Instead of the transport RAM in the traditional architecture, an overlapped row-column operation is used that can reduce the total latency of the pipelined structure. The multiplication is accomplished by using look-up tables and a partial sum adder to reduce the area and cycle time. It possesses no matrix transposition and is suitable for VLSI implementation. We have designed a DCT/IDCT chip using this architecture via the Compass standard cell library under the TSMC 0.35 /spl mu/m 1P4M process. The chip occupies 4278.4 /spl mu/m/spl times/4278.4 /spl mu/m and consists of 119,181 transistors. The simulation results show that a clock rate of up to 100 MHz can be achieved.