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A novel trapping-nitride-storage nonvolatile memory cell by using a gated-diode structure is proposed. An ultrathin nitride layer is introduced between the n-type and p-type regions of the diode. This layer acts as a dopant diffusion barrier that well defines the junction location. Meanwhile, it is thin enough that charge carriers can flow through it via direct tunneling at low field as being sensed. Good program/erase characteristics and acceptable reliability are presented. Finally, using a low-bandgap material to enhance the sensing current is suggested along with the preferred device structure. [ABSTRACT FROM AUTHOR]

A novel programming by hot-hole injection nitride electron storage (PHINES) Flash memory technology is developed. The memory bit size of 0.046 μm2 is fabricated based on 0.13-μm technology. PHINES cell uses a nitride trapping storage cell structure. Fowler-Nordheim (FN) injection is performed to raise Vt in erase while programming is done by lowering a local Vt through band-to-band tunneling-induced hot hole (BTBT HH) injection. Two-bits-per-cell feasibility, low-power and high-speed program/erase, good endurance and data retentivity make it a promising candidate for flash EEPROM technology in gigabit era applications. [ABSTRACT FROM AUTHOR]

A variable-amplitude low-frequency charge-pumping technique is proposed to characterize the nitride-trap energy and spatial distributions in SONOS Flash memory cells. A numerical model based on Shockley—Read—Hall-like electron tunneling capture is used to correlate a charge-pumping current with the nitride-trap energy and position. By changing the frequency and pulse amplitude in charge-pumping measurement, a nitride-trap density, as a function of the trap position and energy, can be extracted. [ABSTRACT FROM AUTHOR]

The cause of over-erasure in a two-bit nitride storage Flash memory cell is investigated. Extra positive charges accumulated above the n+ junction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (Vt) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state Vt distribution, which will reduce overerasure significantly. [ABSTRACT FROM AUTHOR]