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Due to the increasing demand for 3D applications, development of novel depth-sensing cameras is being actively pursued. However, most of these cameras still face the challenge of high energy consumption and slow speed in the depth extraction process. This becomes a serious bottleneck in embedded implementations where real-time performance is required, constrained by power and area. This work proposes Offset Aperture (OA) camera, a new hardware architecture for fast, low-energy, and low-complexity depth extraction. Optimal implementations of pre-processing, cost-volume generation and cost-aggregation are presented. The whole depth-extraction pipeline has been implemented on a Field Programmable Gate Array (FPGA). Overall, a mere 2.8% of bad classification was achieved with the proposed system. Also, the proposed system can process 37 VGA frames per second while consuming 0.224 μJ/pixel. High accuracy, speed and low energy consumption of the proposed OA architecture make it suitable for embedded applications.

We introduce the Dual-aperture (DA) system which is a novel camera based on depth from defocus (DFD). However, conventional method for DA system has an object color dependency problem, which comes from color transition region between objects or textures in an object. This problem is very important because it results in errors in depth map. For this reason, we propose a 2-step process to obtain the improved depth map compared to the conventional method. First is new interpolation method to align the edge in different color channel using IR channel information. Second is the process to adaptively select suitable color channel for the depth extraction. In addition, experimental results indicate that we can obtain the improved depth map only with a small amount of additional computing time, or about 1% of the computing time for the conventional method.

Background subtraction is widely used in battery-operated surveillance system. In the system, memory requirement and computational complexity are important issues due to a constraint of the hardware resource. We propose memory-efficient and low computational complexity background subtraction algorithm based on multi-background registration (MBR) technique algorithm.