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In this work, we demonstrate atomic-layer-deposited (ALD) single-channel indium oxide (In2O3) gate-all-around (GAA) nanoribbon field-effect transistors (FETs) in a back-end-of-line (BEOL) compatible process. A maximum on-state current (ION) of 19.3 mA/ $\mu \text{m}$ (near 20 mA/ $\mu \text{m}$) and an on/off ratio of 106 are achieved in an In2O3 GAA nanoribbon FET with a channel thickness (TIO) of 3.1 nm, channel length (Lch) of 40 nm, channel width (Wch) of 30 nm and dielectric HfO2 of 5 nm. Short-pulse measurements are applied to mitigate the self-heating effect induced by the ultra-high drain current flowing in the ultra-thin channel layer. The record high drain current obtained from an In2O3 FET is about one order of magnitude higher than any conventional single-channel semiconductor FETs. This extraordinary drain current and its related on-state performance demonstrate that ALD In2O3 is a promising oxide semiconductor channel with great opportunities in BEOL compatible monolithic 3D integration. [ABSTRACT FROM AUTHOR]

The role of a HfO2 or ZrO2 interlayer as a thermal bridge between a $\beta $ -Ga2O3 channel and a sapphire substrate was investigated using a $\beta $ -Ga2O3 nano-membrane FET as a test vehicle. A 35% less channel temperature increase was observed when a thin HfO2 or ZrO2 interlayer was inserted between the $\beta $ -Ga2O3 channel and the sapphire substrate compared to devices without interlayers. Phonon density of states (PDOS) mismatch can explain the improvement of the thermal boundary conductance (TBC). In the acoustic region, the PDOS of HfO2 or ZrO2 has about a 700% larger overlap area with the PDOS of $\beta $ -Ga2O3 compared to the PDOS of sapphire. This suggests that the insertion of a thermal bridge interlayer can provide a potential solution to the low thermal conductivity of $\beta $ -Ga2O3 and the self-heating effect of $\beta $ -Ga2O3-based FETs. [ABSTRACT FROM AUTHOR]

In this article, bidirectional control of threshold voltage (${V}_{T}$) is realized in both n- and p-silicon-on-insulator (SOI) nanowire FETs (NWFETs) by using sub-1 nm atomic-layer-deposited (ALD) dipole layers (Y2O3 and Al2O3) for the first time. A 0.7 nm Y2O3 inserted between bottom native SiOx (< 1 nm) and top HfO2 (3 nm) can shift the ${V}_{\text {TH}}$ by −138 and −58 mV for n- and p-NWFET, respectively, while 0.7 nm Al2O3 can shift the ${V}_{T}$ of n-NWFET by +219 mV and p-NWFET by +134 mV. The tunability of such a high-k superstructure for the flat band voltage (${V}_{\text {FB}}$) shift of capacitors and ${V}_{\text {TH}}$ shift of planar n-SOI FETs are also investigated. Furthermore, to concisely control the ${V}_{\text {TH}}$ and ${V}_{\text {FB}}$ as design, capacitors fabricated with quadra-layer (SiOx/HfO2/Al2O3/Y2O3) high-k superstructure were fabricated and 3 mV ${V}_{\text {FB}}$ shift is achieved by carefully adjusting the composition of intermixed-dipole layers. This work points out the route to concisely tune the threshold voltage of complementary metal-oxide-semiconductor (CMOS) FETs with the desired direction and strength. [ABSTRACT FROM AUTHOR]

Recently, back-end-of-line (BEOL) compatible indium oxide (In2O3) thin-film transistors (TFTs), grown by atomic layer deposition (ALD) with channel thickness of ~1 nm and channel length down to 40 nm, have achieved a record high drain current of 2.2 A/mm at ${V}_{\textit {DS}}$ of 0.7 V. A systematic characterization of the reliability issues, such as positive bias temperature stress (PBTS) and hot carrier degradation (HCD), would allow its immediate integration into innovative ICs, such as 3D-stacked SRAM or on-chip bridge for mixed-voltage systems. Surprisingly, PBTS and HCD are both characterized by a universal two-stage threshold voltage shift ($\Delta \!{V}_{\textit {th}}$ , a positive shift followed by a temperature-activated negative shift). This is attributed respectively to electron trapping/trap-generation and hydrogen-assisted formation of donor-traps. These competing mechanisms of $\Delta ~{V}_{\textit {th}}$ depend on the stress voltages and stress temperature. Unlike traditional logic transistors, HCD in BEOL-TFTs is strongly correlated to PBTS, caused by the much stronger vertical field in an ultra-thin device. Overall, this high-performance BEOL-transistor is remarkably reliable, with a relatively small $\Delta ~{V}_{\textit {th}}$ under PBTS/HCD stress conditions at room temperature (RT). However, self- and mutual heating of BEOL interconnect levels and the resultant threshold voltage variability must be mitigated/managed for its successful integration in various neuromorphic circuits. [ABSTRACT FROM AUTHOR]

In this work, indium-tin-oxide (ITO) transistors with atomically thin channel thickness (${T}_{ch}$) of 2.1 nm realized by atomic layer deposition (ALD) are demonstrated. A maximum ON-state current of 970 mA/mm at ${V}_{DS}$ of 0.8 V and an ON/OFF ratio up to 107 are achieved in ITO transistor with In:Sn ratio of 9:1, channel length (${L}_{ch}$) of 60 nm, and dielectric equivalent oxide thickness (EOT) of 2.1 nm. Comparison between devices with different In:Sn ratios indicates a significant reduction of electron transport resulting from more Sn concentrations in ITO. The impact of back-end-of-line (BEOL) compatible low-temperature annealing is also investigated. An enhancement-mode operation with minimum subthreshold slope (SS) of 80 mV/dec and maximum field-effect mobility ($\mu _{FE}$) of 28 cm2/ $\text{V}\cdot \text{s}$ is achieved after O2 annealing. Besides, bias instability measurement shows the negative threshold voltage (${V}_{T}$) shift under both positive and negative gate bias stress due to donor-like interface states below the trap neutral level (TNL). The realization of large-area synthesis of atomically thin ITO films by ALD and decent electrical performance provide opportunities in future monolithic 3-D device integration with BEOL compatibility. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate the record high maximum drain current (${I}_{{\mathrm {D}}}$) of 2 A/mm of top-gate (TG) indium oxide (In2O3) transistors. The scaled and atomic-layer-deposited (ALD) In2O3 transistors have channel length (${L}_{{\mathrm {ch}}}$) down to 40 nm and channel thickness (${T}_{{\mathrm {ch}}}$) down to 1.3 nm. Besides, the thermal budget of the whole material formation and device fabrication process is as low as 225 °C, making it compatible with back-end-of-line (BEOL) technologies by a huge margin. On the other hand, highly resistive silicon is utilized to serve as a desired high thermal conducting substrate to dissipate the generated heat efficiently as a larger current is conducted under a larger voltage bias. It greatly alleviates the self-heating effect (SHE) and allows an approximately 100% higher drain current. Quantitative studies of the SHE and channel temperature at ON-state with SiO2/Si and highly resistive silicon substrates are also presented. [ABSTRACT FROM AUTHOR]

In this work, we report the experimental demonstration of In2O3 3-D transistors coated on fin structures and integrated circuits by a back-end-of-line (BEOL) compatible atomic layer deposition (ALD) process. High-performance planar back-gate In2O3 transistors with high mobility of 113 cm2/ $\text{V}\cdot \text{s}$ and high maximum drain current (${I}_{\rm D}$) of 2.5 mA/ $\mu \text{m}$ are achieved by channel thickness engineering and postdeposition annealing. The high-performance ALD In2O3-based zero- ${V}_{\rm GS}$ -load inverter is demonstrated with a maximum voltage gain of 38 V/V and a minimum supply voltage (${V}_{\rm DD}$) down to 0.5 V. Top-gate indium oxide (In2O3) transistors by low-temperature ALD of both gate insulator and channel semiconductor are also demonstrated with ${I}_{\rm D}$ of $570~\mu \text{A}/\mu \text{m}$ and low subthreshold slope (SS) down to 84.6 mV/decade. ALD In2O3 3-D Fin transistors with the top-gate structure are then demonstrated, benefiting from the conformal deposition capability of ALD. These results suggest that ALD oxide semiconductors and devices have unique advantages and are promising toward BEOL-compatible monolithic 3-D integration for 3-D integrated circuits. [ABSTRACT FROM AUTHOR]

Coupled-oscillatory networks are an emerging paradigm for efficiently solving optimization problems. In this work, we demonstrate the application of ferroelectric field-effect transistor (FeFET) for energy-efficient coupled-oscillatory networks. A CMOS-compatible FeFET was fabricated having > 1V of hysteresis window and 57 mV/dec of minimum subthreshold swing. With our proposed FeFET oscillator circuits and optimized biasing schemes, a $2\times $ wider synchronization range and up to $276\times $ lower energy per cycle were achieved compared to previous FeFET-based oscillators. Moreover, we employ FeFET coupled-oscillatory network for an edge detection task. Our simulations considering FeFET non-idealities and process variations with a 5-bit quantized image show that the edge detection output closely follows the ideal output. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistors (Fe-FETs) with ferroelectric hafnium oxide (FE HfO2) as the gate insulator are being extensively explored as a promising device candidate for non-volatile memory application. FE HfO2 exhibits long retention over ten years, high endurance over 1012 cycles, high speed with subnanosecond polarization switching, and high remnant polarization of 10– $30~\mu \text{C}$ /cm2. However, the performance of Fe-FETs is known to be much worse than FE HfO2 capacitors, which is not completely understood. In this work, we developed a comprehensive Fe-FET model based on a charge balance framework. The role of charge balance and the impact of leakage-assist-switching mechanism on the memory characteristics of Fe-FETs with Metal/Ferroelectric/Dielectric/Semiconductor (M/FE/DE/S) gate-stack is studied. It is found that the ferroelectric/dielectric (FE/DE) interface and DE layer instead of FE layer is critical to determine the memory characteristics of Fe-FETs, and experimental Fe-FETs can be well explained by this model, where the discrepancy between FE capacitors and Fe-FETs are successfully understood. [ABSTRACT FROM AUTHOR]

In this work, we report back-end-of-line (BEOL) compatible indium-tin-oxide (ITO) transistors with ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) as gate insulator. A tunable high-density 2-D electron gas over 0.8 × 1014/cm2 is achieved at the HZO/ITO oxide/oxide interface because of the FE polarization, which is confirmed by I – V, positive up and negative down (PUND), and Hall measurements. Such high carrier density can be completely modulated and switched on and off by FE polarization switching, enabling high mobility ITO transistor with high ON-current and high ON/OFF ratio. [ABSTRACT FROM AUTHOR]

We have experimentally demonstrated robust beta-gallium oxide (β-Ga2O3) ferroelectric (FE) field-effect transistors (FeFETs) on a sapphire substrate operated up to 400 °C. Atomic layer deposited (ALD) Hf0.5 Zr0.5O2 [hafnium zirconium oxide (HZO)] is used as the FE dielectric. The HZO/β-Ga2O3 FeFETs are studied for their synaptic behavior applications at elevated temperatures. The devices show distinguishable polarization switching operation with the output conductance quasi-linearly controlled by the number of input pulses on the FE gate. In a simulation, on-chip learning accuracy reaches 94% at elevated temperatures using the Modified National Institute of Standards and Technology (MNIST) data set with a simple two-layer multilayer perceptron (MLP) network. These ultra wide bandgap semiconductor devices have the potential to fill the need for harsh environment neuromorphic applications. [ABSTRACT FROM AUTHOR]

The ferroelectric (FE) polarization switching behavior in the HfZrO2 (HZO) FE/dielectric (FE/DE) stack is investigated systematically by charge responses from pulse measurements. The trapped charge density at the FE/DE interface related with the FE polarization switching is found to be 1.2 × 1014 cm−2 according to the leakage-current-assist polarization switching mechanism. Furthermore, by the time-dependent nonswitching charge responses, the extra FE/DE interface trap density of 1.1 × 1013 cm−2 is confirmed, which is not related but can be detected along with the FE polarization switching. The quantitative characterization reveals the huge amount of FE/DE interface traps and their dominant role in the FE operation of HZO FE/DE stack, which improves the proposed leakage-current-assist polarization switching model. This improved model provides a more comprehensive understanding of the polarization switching in the HZO FE/DE stack and new insights on HZO negative-capacitance (NC) and FE field-effect transistors (FETs). [ABSTRACT FROM AUTHOR]

In this article, we demonstrate atomic-layer-deposited (ALD) indium oxide (In2O3) transistors with a record high drain current of 2.2 A/mm at VDS of 0.7 V among oxide semiconductor transistors with the enhancement-mode operation. The impact of back-end-of-line (BEOL) compatible low-temperature annealing is systematically studied on these highly scaled In2O3 transistors with channel length (Lch) down to 40 nm, channel thickness (Tch) down to 1.2 nm, and equivalent oxide thickness (EOTs) of 2.1 nm, at annealing temperatures from 250 °C to 350 °C in N2, O2, and forming gas (FG, 96% N2/4% H2) environments. Annealing in all different environments is found to significantly improve the performance of ALD In2O3 transistors, resulting in enhancement-mode operation, high mobility, reduced bulk and interface trap density (Dit as low as 6.3 ×1011 cm−2 ⋅ eV−1), and nearly ideal subthreshold slope (SS) of 63.8 mV/dec. Remarkably, the ALD In2O3 devices are found to be stable in hydrogen environment, being less affected by the well-known hydrogen doping issue in indium–gallium–tin-oxide (IGZO). Therefore, low-temperature ALD In2O3 transistors are highly compatible with the hydrogen-rich environment in BEOL fabrication processes. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate scaled back-end-of-line (BEOL) compatible indium oxide (In2O3) transistors by atomic layer deposition (ALD) with channel thickness (Tch) of 1.0-1.5 nm, channel length (Lch) down to 40 nm, and equivalent oxide thickness (EOT) of 2.1 nm, with record high drain current of 2.0 A/mm at VDS of 0.7 V among all oxide semiconductors. Enhancement-mode In2O3 transistors with ID over 1.0 A/mm at VDS of 1 V are also achieved by controlling the channel thickness down to 1.0 nm at atomic layer scale. Such high current density in a relatively low mobility amorphous oxide semiconductor is understood by the formation of high density 2D channel beyond $4\times 10^{13}$ /cm2 at HfO2/In2O3 oxide/oxide interface. [ABSTRACT FROM AUTHOR]

In this work, the conductance method with an optimized circuit model is established to investigate the trapped charges at the ferroelectric/dielectric (FE/DE) interface. The density of interface states is quantitatively characterized to be ~4 × 1012 to 1013 cm−2 ⋅ eV−1. And the injection and accumulation of these enormous interfacial charges play a key role in the operation of the FE/DE stack. The proposed measurement technique provides a comprehensive understanding of the FE/DE stack as well as some new insights of negative capacitance effect and ferroelectric field-effect transistor device operations. [ABSTRACT FROM AUTHOR]

In this paper, we report the experimental extraction of ballistic transport parameters of high-performance Germanium Nanowire nMOSFETs (Ge NWTs) with lengths ${L}_{\text {NW}} = {40}$ –100 nm, width ${W}_{\text {NW}} = {40}$ nm, and height ${H}_{\text {NW}} = {10}$ nm using temperature-dependent measurements. The extracted contact resistivity ($\rho {c}$) and sheet resistance (Rsh) imply that parasitic series resistance (${R}_{\text {SD}}$) of fabricated Ge NWTs is affected by $\rho _{c}$ of the metal-nGe (${3.42} \times {10}^{-{5}}\,\,\Omega \cdot \text {cm}^{{2}}$ at 292 K), which decreases with the increase in temperature. Ballistic efficiency (BE) is found to be 22%–47% at 292 K depending on the dimension of the device. It decreases with increased temperature and increases with ${L}_{\text {NW}}$ scaling down to 40 nm. The transition region with fluctuating BE is observed near ${L}_{\text {NW}} = {50}$ –60 nm, where the electron transport enters deeper into bthe allistic regime. BE is found to be sensitive to temperature and drops from 58% (170 K) to 37% (390 K) for ${L}_{\text {NW}} = {40}$ -nm Ge NWT. Therefore, in order to maintain the high ballisticity of the devices, it is important to optimize the device structure and eliminate the self-heating effect. [ABSTRACT FROM AUTHOR]