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We present a novel cavity engineering work – we named this cavity as dual-curvature cavity, which improves pFET electrical performance. This new cavity shape design minimizes the source/drain leakage penalty from deeper cavity depth while enabling the transistor performance benefits from larger eSiGe. In addition, this new cavity shape minimizes the penalty of deeper cavity on SDB (single diffusion break) devices through minimizing the facet effect in SDB structure. This work demonstrates that this new cavity shape could improve p-type transistor performance by 4{\%} on top of the Fin shape optimization.

As the size of the semiconductor device continues to shrink, two integration approaches are used for gate module; (1) gate first, and (2) gate last. The gate last approach requires removal of thin (10–30Å) titanium nitride (TiN) diffusion blocking layers during the “replacement” process after the poly-Si layer is removed. An etch rate study was conducted to evaluate the selectivity of a combined aqueous/solvent cleaning chemistry at various temperatures on blanket TiN and TaN wafers to identify the optimum operating regime. A significant improvement of yield with the application of the new cleaning approach has been observed.