Search

Your search keyword '"Yamashita T"' showing total 568 results

Search Constraints

Start Over You searched for: Author "Yamashita T" Remove constraint Author: "Yamashita T" Publisher ieee Remove constraint Publisher: ieee
568 results on '"Yamashita T"'

Search Results

2. Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling

4. Pixel Pitch Hybrid Bonding and Three Layer Stacking Technology for BSI Image Sensor

5. Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices

6. Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation

8. Sub-6V Operation of Split-Gate Type Charge-Trapping Nonvolatile Memory with High-k Trapping and Blocking Layers for High-Speed and HighlyReliable Embedded Flash

11. Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

13. Co-Existence of 87 Mbit/s Quantum and 10 Gbit/s Classical Communications in 37-Core Fiber

14. 13.1 A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology

15. Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs Beyond 7nm

18. Reliability and scalability of FinFET split-gate MONOS array with tight Vth distribution for 16/14nm-node embedded flash

23. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

25. A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

26. Air spacer for 10nm FinFET CMOS and beyond

27. FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys

28. FINFET technology featuring high mobility SiGe channel for 10nm and beyond

30. Ti and NiPt/Ti liner silicide contacts for advanced technologies

31. Process optimizations for NBTI/PBTI for future replacement metal gate technologies

33. Understanding and mitigating High-k induced device width and length dependencies for FinFET replacement metal gate technology

37. A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs

41. FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

44. Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs

45. Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs

49. Channel doping impact on FinFETs for 22nm and beyond

Catalog

Books, media, physical & digital resources