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A type-II analog phase-locked loop without charge pump and analog loop filter is proposed in this paper. A novel discrete proportional-integral-derivative circuit (DPIDC) is proposed to implement phase error integration and frequency compensation with time-domain processing. A phase-to-voltage converter (PVC) with a sample-and-hold is used to convert the phase error processed by the DPIDC to a voltage that controls the voltage-controlled oscillator (VCO). Simulation results in 180nm CMOS technology show the proposed DPIDC and PVC circuits only consume 6.5-µW power at 0.6-V supply voltage. The proposed PLL settles down steadily and achieves a normalized reference-spur rejection better than -84.6dBc.

Operational transconductance amplifiers (OTAs) are widely employed as active elements in filters, data converters, and buffer amplifiers. Inverter-based implementation of OTAs is an attractive approach for low voltage realization of analog subsystems. However, there are still fundamental challenges such as how to simultaneously achieve high DC gain, bandwidth, speed, and good noise performance based on existing inverter-based OTA architectures. In this paper, a new two stage OTA, hybrid with current reuse inverter OTA and Nauta transconductor is proposed to improving performance by taking advantages of their own merits. The introduced architecture is keeping the merits of Nauta transconductor such as high bandwidth, high speed and the superior input referred noise performance of the current reuse inverter-based OTA. Furthermore, in order to reduce the PVT variations, bulk tuning circuits based on "detecting-feedback" loop applied on CMFB and the output stage of Nauta transconductor is proposed to dynamically tune the output DC levels under PVT variations. The proposed new hybrid OTA is implemented in 180nm CMOS technology and achieves very competitive performance compares with all inverter based OTAs and the other state-of-the-art OTAs.

This paper presents a new high speed, high conversion gain envelope detector (ED) using dynamic load (DL) and 2nd order nonlinearity maximization techniques. To enhance the conversion gain and speed of conventional ED architectures, the proposed ED uses a dynamic load (DL) technique with class-AB architecture to increase the speed and tune the output impedance dynamically. To improve nonlinearity of the ED, derivative superposition (DS) is used. By biasing the NMOS and PMOS transistors of the ED initially in different regions of operation, 2nd order derivative of transconductance (g2) is maximized which increases the 2nd order conversion gain. This configuration enables low power consumption without compromising the conversion gain. Simulation results of the proposed ED in 0.18μm CMOS technology show a high data rate of 14.5Mbps with power consumption of 1.21μW.

DC-DC buck converters with high conversion efficiency are widely used in ultralow power applications. This paper proposes a new method of power metal-oxide-semiconductor field-effect transistors (MOSFETs) size optimization for DC-DC buck converters based on optimum power efficiency. It analyses the power loss of DC-DC buck converters and presents an equation describing the relationship between their power MOSFETs size and their power efficiency. In addition, a method is proposed for optimizing the power MOSFETs size of DC-DC buck converters. This method is validated by simulation result from MATLAB and implemented in a 0.35 $\mu\mathbf{m}$ CMOS process. The power efficiency of the DC-DC buck converter was scanned for different power MOSFETs sizes at an input voltage of 3.6 V and a load current of 300 mA, and the optimum size (based on optimum power efficiency) is obtained. The results of this simulation verify the accuracy of the power MOSFETs size optimization methods.

Using pure electric voltages instead of magnetic fields or large currents to manipulate magnetisms in multiferroic heterostructures is a goal for future low-power spintronics such as electric-writing magnetic-reading memories. Usually, the electric manipulation to magnetism shows a volatile effect which cannot be used for information storage,[1] because the magnetic variation vanishes after the electric field removal. Recently, the piezostrain-mediated non-volatile 90° and 180° magnetization rotations are realized in the Co/0.7Pb(Mg 1/3 Nb 2/3 )O 3 -0.3PbTiO 3 multiferroic heterostructures at room temperature.[2] However, the non-volatile magnetization rotations in perovskite manganese systems, which are of significance for the design of perovskite magnetic random access memories such as perovskite magnetic tunneling junctions, are still rarely studied. Here we report an in-situ electric field manipulated nonvolatile and reversible 900-rotation of the magnetic easy-axis (MEA) in La 0.7 Sr 0.3 MnO 3 /0.7Pb(Mg 1/3 Nb 2/3 )O 3 -0.3PbTiO 3 (LSMO/PMN-PT) multiferroic heterostructure.

In the mixed states of type II superconductors, one of the most fascinating research topics is the vortex phase transition from a vortex-glass phase to a vortex liquid phase with variations of temperatures or magnetic fields.[1] Recently, the discovery of iron-based superconductors opens a new route to investigate the phase transition. However, the influence of magnetic field orientation on the vortex glass (VG) transition in iron-based superconductors has not been studied in detail yet.