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This paper presents two novel singly-fed circularly polarised (SFCP) patch antennas at 2.45 GHz. Unlike the traditional ones, the patches are loaded by two pairs of parallel slots, acted as negative perturbation. The antennas are fed by using different capacitive feeding mechanisms, direct soldering against indirect coupling. Their performances are compared.

Though being accepted and widely employed for decades, there remains no consensus in the industry on the selection of an optimum temperature profile for the accelerated temperature cycling (ATC) test for the evaluation of board level solder joint reliability. It is generally agreed that broader temperature range and higher mean temperature should result in shorter thermal fatigue life. Yet, people have different opinions on the selection of the ramp rate and the dwell time. It was believed that the ramp rate has little influence on the solder joint thermal fatigue life. Emphasis has been put on the design of a suitable dwell time. Therefore, the JEDEC and the IPC standards did not impose strict requirements on the selection of the ramp rate. On the other hand, a certain range of dwell times were recommended. Nevertheless, there were publications showing that the ramp rate may be important and, in some situations, may even overrule the dwell time. This study attempts to investigate in detail the creep damage accumulation inside the solder joint during the ramp time and the dwell time for all practical loading conditions. Based on numerous computational simulation results, the present study reveals that there actually exist two types of creep damage accumulation. One of them corresponds to a “mild” loading condition where the creep damage is mostly accumulated during the dwell time. Another one corresponds to a “severe” loading condition in which the ramp time contributes most of the creep damage accumulation.

This study serves to validate the predictive finite element modeling approach for the solder joint thermal fatigue life analysis, with emphasis on the applicability to various lead-free solder joints. The three packages involved in the study are 8×8 mm PBGA, l0×l0 mm QFN, and 51×51 mm CBGA. They are designed to consist of SAC387, SAC305, “SAC305 ball + SAC387 paste” and “SAC387 ball + SAC305 paste” solder joints. ATC tests are performed to determine the characteristic lives of these packages. On the other hand, finite element models are developed for these test vehicles. They serve to evaluate the damage of each package, as represented by the creep strain or the creep strain energy density, accumulated during the ATC test. As demonstrated from this work, the commonly adopted power law correlation, which links the numerically calculated damage parameters with the experimentally determined characteristic lives, can be used for the solder joint thermal fatigue life prediction, even for the case with mixed solder alloys.

Cracking of the silicon chip of a wafer level chip scale package (WLCSP) is encountered during a thermal cycle test (TCT). This paper attempts to examine the failure mechanism. Both numerical and experimental efforts were devoted to investigate the problem. A series of finite element models with different combinations of material properties and geometric configurations were developed. The results showed that both the under bump metallization (UBM) and the dielectric layer Benzocyclobuten (BCB) contributed significantly to the stress level induced inside the silicon chip. In addition, solder ball pull tests were performed. The silicon cratering failure mode was reproduced which confirmed the failure mechanism as proposed by the finite element analysis. The effects of all relevant constituent materials on the chip are discussed in detail. Suggestions for the product design improvement are provided at the end of the paper.

The objective of the present study is to develop a robust high-throughput assembly process of light emitting diode arrays for wide area general lighting. Topics to be covered in this paper include the conceptual design, the flexible printed circuit substrate, flip chip assembly, yellow phosphor coating, and encapsulation. All these are integrated into one reel-to-reel assembly process. A prototype with the proposed process has been developed. A sample strip of packaged LED array has been produced as well to validate the developed assembly process.

The objective of the present study is to develop a robust high-throughput assembly process of light emitting diode arrays for wide area general lighting. Topics to be covered in this paper include the conceptual design, the flexible printed circuit substrate, flip chip assembly, yellow phosphor coating, and encapsulation. All these are integrated into one reel-to-reel assembly process. A prototype with the proposed process has been developed. A sample strip of packaged LED array has been produced as well. Recommendations for future industrial applications are also provided.

This paper evaluates the thermal performance of a newly developed multi-stack flip chip package using the finite element method. The effect of the major parameters, identified as the solder material, the solder joint pitch, the solder joint height and the pad diameter on the thermal performance of the package is studied. Based on the finite element results, a lumped model is developed which is capable to give quick and promising results of the junction temperatures of the package for different solder joint configuration.