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A 1.25-Gbit/s optical transceiver module for GE-PON system was developed. We devised a low-noise TIA and a LIM with a high-speed response for the receiver using a PIN-PD. This transceiver enables us to construct a low-cost PON system with high quality.

A 1.25-Gbit/s burst-mode optical receiver for access networks was developed. We devised transimpedance amplifier (TIA) and limiting amplifier (LIM) circuits using a PIN-PD instead of an APD, and the receiver exhibits high sensitivity of -30 dBm.

A series-connected voltage-balancing circuit can output n-times larger voltage swing than can be output by a single transistor, where n is the number of series-connected transistors. This circuit makes it possible for high-speed low-breakdown-voltage transistors to be applied to large-voltage-swing pulse drivers, such as an optical modulator driver. This paper reports the first operation of this type of driver at 10 Gbit/s. Novel direct-coupled current switch architecture prevents FETs exceeding gate-drain breakdown voltage and keeps high-speed operation. The fabricated driver demonstrated 3.7 V/sub pp/ (7.4 V/sub pp, diff/) output with clear eye opening.

A new network analyzer based on ultrafast optoelectronic techniques is presented. It uses integrated and packaged mm-wave-photonic active probes and enables on-wafer measurements of scattering parameters with a bandwidth exceeding 300 GHz.

This paper proposes a hybrid position/force control of a mobile manipulator to cooperate with its subsystems that consist of a wheeled mobile robot and a manipulator arm. These subsystems have different dynamic characteristics. Moreover, a wheeled mobile robot is subject to nonholonomic constraints. In general, these issues are taken into consideration in developing a planning and control algorithm. This paper describes a unified approach to control a mobile manipulator which can be regarded as a redundant manipulator. In the proposed approach, realizing an optimal configuration control according to the motion of the end-effector, the redundancy of the proposed system is utilized under consideration of the dynamical behavior of the mobile manipulator. Several experimental results show the effectiveness of the proposed method.

The relationship between the size of plastic internal cracks and the extent of plastic delamination was investigated by using scanning acoustic tomography and visual cross-sectional inspection. Plastic internal cracks grow larger as plastic delamination spreads during consecutive moisture/solder reflow process stress tests. The effect of die pad size on plastic package cracking induced by the moisture/solder reflow process was studied. It was found that the extent of package cracking decreased with longer die pads due to the venting effect of the support pin. A package design that demonstrates good performance with respect to package cracks is presented. >

High-yield and high-performance digital/analog ICs have been fabricated using the same InAlAs/InGaAs/InP-HEMT process. SCFL static frequency dividers show a fabrication yield of 63% and operate at 36.7/spl plusmn/0.55 GHz. Two-stage MMIC LNAs show a yield of 75% and at 62 GHz a noise figure of 4.3/spl plusmn/0.19 dB and a gain of 11.8/spl plusmn/0.25 dB.

This paper proposes a new systematic approach to the noise-figure (NF) sensitivity analysis of MMIC low-noise amplifiers (LNA) regarding device structure parameters such as gate-recess variation for the first time. A full-monolithic uniplanar two-stage LNA with an extremely low NF of 2.8 dB at 50 GHz is fabricated and analyzed using this new method. A comparative study reveals that the gate recess variation in the fabricated HEMTs causes no substantial NF variation in the MMIC-LNAs. >

A wideband amplifier operating from dc is indispensable for waveform processing such as data signal amplification in optical transmission systems. There are two serious problems in widening the bandwidth of the amplifier IC. One is the chip mounting, where the wavelength of the electrical signal approaches the physical size of the mounting elements such as the package cavity, input/output leads, bonding wires and so on. Therefore, the three-dimensional distributed effects of these elements must be controlled in the circuit design for stable amplifier operations. The other is the circuit configuration of the amplifier. Amplifiers designed using the lumped-constant theory have a bandwidth restriction caused from parasitic capacitance. On the other hand, a distributed amplifier is capable of eliminating this restriction. A suitable package is based on the concept of "a chip-size cavity package", by which the parasitic resonance is suppressed and the isolation characteristics between input and output ports are greatly improved. Second, a frequency-dependent biasing termination is employed for the drain-line of the amplifier to improve gain degradation at frequencies below 1OGHz. >

In this paper, we report the fabrication and the device characteristics of the InP-based lattice-matched HEMTs with a 30-nm gate, which is the smallest gate yet achieved for InP-based HEMTs. A fullerene-incorporated nanocomposite resist is used in electron beam (EB) lithography to achieve such a small gate. A cutoff frequency of the 30-nm-gate HEMTs is 350 GHz, which is comparable to the reported value for 50-nm-gate InP-based pseudomorphic HEMTs and one of the highest value achieved by any kind of three-terminal electronic device.

A novel approach for making high-performance enhancement-mode InAlAs/InGaAs HEMTs (E-HEMTs) is described. Most important for the fabrication of E-HEMTs is the suppression of the parasitic resistance due to side-etching around the gate periphery during gate recess etching. Two-step-recessed gate technology is utilized for this purpose. The first step of the gate recess etching removes cap layers wet-chemically down to an InP recess-stopping layer and the second step removes only the recess-stopping layer by Ar plasma etching. Etching selectivities for both steps are sufficient not to degrade the uniformity of devices on the wafer. The resulting structure achieves a positive threshold voltage of 49.0 mV with high transconductance. Due to the etching selectivity, the standard deviation of the threshold voltage is as small as 13.3 mV on a 3-inch wafer. A cutoff frequency of 208 GHz and a maximum frequency of oscillation of 460 GHz are obtained for the 0.1-/spl mu/m-gate E-HEMTs. This technology for E-HEMTs is a promising candidate for ultra-high-speed applications.

The authors propose a new method to evaluate the human interface design of nuclear power plant equipment from the viewpoint of human error. Their system, called DIAS, is implemented on a workstation and consists of a maintenance personnel model and an equipment interface model. The maintenance personnel model stores the standard maintenance procedures which are represented by the augmented Petri net model. The authors consider the visual field, walking speed and the focal/peripheral working memory in the maintenance personnel model. DIAS analyzes the potential human errors of each task in the simulation results by using the human-error-mechanism knowledge base combined with a quantitative human error rate prediction technique. The equipment interface model can be easily redesigned on the graphical editor, which enables the analyst to evaluate alternative designs. They applied this system to evaluate the interface design of the actual GIS protection relay panels and their layout in the nuclear power plant.

This paper describes the design and performance of an 80-Gbit/s 2:1 selector-type multiplexer IC fabricated with InAlAs/InGaAs/InP HEMTs. By using a double-layer interconnection process with a low-dielectric insulator, microstrip lines were designed to make impedance-matched, high-speed intercell connection of critical signal paths. The record operating data rate was measured on a 3-in wafer. In spite of the bandwidth limitation on the measurement setup, clear eye patterns were successfully observed for the first time. The obtained circuit speed improvement from the previous result of 64 Gbit/s owes much to this high-speed interconnection design.

Forty-GHz operation of SCFL static binary frequency dividers is demonstrated by monolithically integrating 0.1-/spl mu/m-gate InAlAs/InGaAs HEMTs and p-n diodes for the first time. The HEMT has an InP-recess-etch stopper in the InAlAs barrier and the standard deviation of the threshold voltage in a 2-inch wafer is reduced to 44 mV. The p-n diode is used as a level-shift diode because of its smaller size and lower resistance than those of conventional diodes using a Schottky gate of the HEMT. The reduced resistance and size result in shorter CR-time delays of the diodes and transmission delays of the interconnection. Thus, it is possible to make the most of high-speed performance of the HEMTs in the circuits by employing p-n diodes as level-shift diodes.

This paper investigates capability of following technologies; mold compound, die attach adhesive, textured die pad, and buffer coat, in resolving or improving the package crack performance of plastic package during reflow soldering process. We have finally succeeded in resolving this problem by making a die pad smaller than chip size and analyzed the stress, thermal and electrical characterization by using the simulation to determine suitable scoop size and lead frame line-up. The chip size limitation was confirmed by actual experiments for a chip size, a package size and a package thickness.

We analyzed the bias-voltage dependence of the 1/f like drain-noise current of highly biased InGaAs-based lattice-matched HEMTs and evaluated the effective length of the high-field region at the drain edge of the device. We found that the effective length was between the nominal barrier thickness and the estimated lateral extension of side-etched region, and that the effective length increased when the gate bias voltage was decreased. This work is likely to provide a semi-quantitative method for determining experimentally the effective length of the high-field region of these HEMTs.

Argumentation is a computing principle in the new era of information processing, and is a unified approach to technologies needed in agent-oriented computing that is based on the societal view of computation, where social concepts play important roles in computation. We show the potential usefulness and feasibility of argument-based agent systems by applying them to a variety of application domains.

A uni-traveling-carrier photodiode (UTC-PD), featuring high-output power and a fast response, was monolithically integrated into a 0.1-/spl mu/m-gate InP-based HEMT digital IC that can operate at over 40 Gbit/s. In the digital OEIC fabrication using our integration technology, the demultiplexing function of an optical-input D-type flip-flop (D-FF) circuit using 40-Gbit/s return-to-zero (RZ) optical signal and 20-GHz electrical clock signal was confirmed. This integration technology enables the development of a simplified receiver unit with high performance for use in 40-Gbit/s and over TDM systems.