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This paper presents improvements in performance, power, and area (PPA) obtained by optimizing the gear ratio (GR) between the Gate and vertical metal layer pitches in standard cells in sub-10nm node CMOS SoC designs. Changing the GR from 1:1 to 3:2 leads to better pin accessibility, routability, and higher cell density. This in turn enables a gate pitch relaxation and associated improvements in cell delay. Implementation of 3:2 GR ultra-dense cells in an SoC CPU block results in up to 17% higher performance, 4% smaller logic size, and 8% lower dynamic power at typical PVT conditions.

Design technology co-optimization (DTCO) is the term used to describe the process of deriving a competitive technology definition out of a number of increasingly complex trade-offs. DTCO is not a specific approach or methodology, but rather a commitment to closer collaboration between designers and process engineers born out of necessity to maintain value in semiconductor scaling. This paper aims to clarify this abstract concept through a series of examples encountered in scaling a logic cell from the N14 to the N3 technology node.