1. Design of High-speed CMOS Frequency Dividers for RF Receiver
- Author
-
Yong Xu, Zhigong Wang, Zhi-Qun Li, Xiao-Hu He, and Lu Tang
- Subjects
Engineering ,Dual-modulus prescaler ,business.industry ,Frequency band ,Hardware_PERFORMANCEANDRELIABILITY ,Chip ,Frequency divider ,CMOS ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,Electronic design automation ,DVB-T ,business ,Operating speed - Abstract
A divide-by-16/17 dual-modulus prescaler (DMP) and two programmable & plus swallow dividers for application in a digital video broadcasting-terrestrial (DVB-T) receiver are designed in a 0.18mum 3.3V mixed-signal CMOS process. The master/slave D-flip-flop (DFF) in the DMP is made up of an improved D-latch to increase the speed and the driving capability. A novel D-latch architecture integrated with 'OR' logic is proposed to decrease the complexity of the circuit. Post simulation results of the chip layout indicate that the proposed DMP works well at the frequency band of 1~2 GHz. The maximum operating speed is 2.4 GHz. The programmable & plus swallow dividers are directly synthesized by EDA tools and finally fabricated with 0.18 mum standard library.
- Published
- 2007