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This paper presents a two-point modulator architecture which is immune to the nonlinear effect of the digitally-controlled oscillator (DCO). By utilizing a 1 bit ΔΣ modulation with embedded finite-impulse response (FIR) filtering the high-pass modulation path does not suffer from the DCO gain nonlinearity, thus requiring absolute gain calibration only. The digital FIR filter in the high-pass modulation path not only suppresses quantization noise but also reduces noise coupling with time-interleaved switching of partitioned capacitors. A hybrid FIR filtering method is also employed for the low-pass modulation path to enhance the linearity of the fractional-N phase-locked loop (PLL). A 1.8 GHz two-point modulator based on a semi-digital PLL is implemented in 65 nm CMOS consuming 6.9 mW from a 1 V supply. At the divide-by-2 output frequency of 913.2 MHz, the error-vector magnitude (EVM) values of 1.79% and 1.63% are achieved with 1.08 Mb/s and 270 kb/s GMSK modulation respectively. When the 1.08 Mb/s GFSK modulation is performed with the same PLL parameters, the EVM value of 1.96% is achieved. [ABSTRACT FROM AUTHOR]

A low-jitter and low-power source-synchronous serializer/deserializer transmitter (TX) with a data rate of 9.6 Gb/s is presented. The TX consists of five data channels plus one forwarded-clock channel and features a total jitter of 20.39 ps p-p at 10^-12 bit error rate. Low jitter is achieved through the use of a phase-locked loop with bandwidth linearization that has a random RMS jitter of 0.66 ps. A global clock distribution network is proposed to minimize the power-supply-induced jitter and the power consumption. The TX transmits preemphasized data through a current-mode logic driver with a four-tap feedforward equalizer. The on-chip output impedance and the signal amplitude can be accurately calibrated by a successive approximation register logic separately. The total power consumption for the 5 $+$ 1-lane TX physical core fabricated in 65-nm bulk CMOS running at 9.6 Gb/s is 230 mW or 4.8 mW/Gb/s. [ABSTRACT FROM PUBLISHER]

A 2 GHz two-point modulator which has a separate high-pass control for DCO modulation is implemented in 0.18 \mum CMOS. The proposed modulator with the two-path DCO modulation enables a flexible gain partition for the high-pass and low-pass modulation paths within the DCO and relaxes the DCO nonlinearity with 1-b \Delta\Sigma modulation and embedded finite-impulse response (FIR) filtering. A semi-digital \Delta\Sigma PLL with another FIR filtering in the low-pass modulation enhances PLL linearity with a hybrid loop control. The proposed semi-digital modulator achieves 2.03% RMS EVM with 2 Mb/s GFSK modulation, -132 dBc/Hz phase noise at 3 MHz offset, and -80 dBc reference spur. [ABSTRACT FROM PUBLISHER]

A 1.1 GHz semi-digital fractional-N PLL without the time-to-digital converter (TDC) whose resolution and linearity heavily depends on process and temperature variations is implemented in 65 nm CMOS. A hybrid loop control with a fully differential proportional-gain path and embedded finite-impulse response (FIR) filtering achieves linear phase tracking as well as good technology scalability, having a small analog loop filter area less than 0.01 mm^2. The use of the hybrid FIR filter not only suppresses out-of-band quantization noise of the \Delta\Sigma modulator but also improves the linearity of the proportional-gain path. The TDC-less semi-digital PLL consumes 1.75 mW from a 0.9 V supply voltage, achieving significant power reduction compared to conventional all-digital PLLs. [ABSTRACT FROM PUBLISHER]