72 results on '"Wu, J.Y."'
Search Results
2. A 40nm Low-Power Logic Compatible Phase Change Memory Technology
3. FinFET IO Device Performance Gain with Heated Implantation
4. Dynamic Load Transfer of Active Distribution Network Based on Prediction Information
5. Ultra low p-type SiGe contact resistance FinFETs with Ti silicide liner using cryogenic contact implantation amorphization and Solid-Phase Epitaxial Regrowth (SPER)
6. A novel self-converging write scheme for 2-bits/cell phase change memory for Storage Class Memory (SCM) application
7. Greater than 2-bits/cell MLC storage for ultra high density phase change memory using a novel sensing scheme
8. A Procedure to Reduce Cell Variation in Phase Change Memory for Improving Multi-Level-Cell Performances
9. A novel inspection and annealing procedure to rejuvenate phase change memory from cycling-induced degradations for storage class memory applications
10. Study on the influence of implant dose rate and amorphization for advanced device characterization
11. A double-density dual-mode phase change memory using a novel background storage scheme
12. Towards the integration of both ROM and RAM functions phase change memory cells on a single die for system-on-chip (SOC) applications
13. Impact of gallium implant for advanced CMOS halo/pocket optimization
14. A high performance phase change memory with fast switching speed and high temperature retention by engineering the GexSbyTez phase change material
15. A low power phase change memory using thermally confined TaN/TiN bottom electrode
16. Integrated NiSi defect reductions in 45nm node and beyond
17. The impact of hole-induced electromigration on the cycling endurance of phase change memory
18. Flatband voltage tuning and EOT reduction for SiO2/HfO2/TiN gate stacks via lanthanum oxide capping layers using two different lanthanum precursors
19. Understanding amorphous states of phase-change memory using Frenkel-Poole model
20. Advances on 32nm NiPt Salicide process
21. Mechanisms of retention loss in Ge2Sb2Te5-based Phase-Change Memory
22. Outage Probability Analysis for Collocated Spectrum-Sharing Macrocell and Femtocells.
23. Mitigating eSiGe strain relaxation using cryo-implantation technology for PSD formation.
24. Investigation of the structural and electrical characterization on ZrO2 addition for ALD HfO2 with La2O3 capping layer integrated metal-oxide semiconductor capacitors.
25. The TDDB failure mode and its engineering study for 45nm and beyond in porous low k dielectrics direct polish scheme.
26. Advances on NiPt SALICIDE process optimization for 28nm CMOS manufacturing.
27. A novel hydrogen rich interfacial layer to downscale high-K dielectrics.
28. Advances on 32nm NiPt Salicide process.
29. A New Vehicle Detection Approach in Traffic Jam Conditions.
30. Artificial Immune System for Solving Constrained Global Optimization Problems.
31. A Novel Programming Model and Optimisation Algorithms for WCDMA Networks.
32. Mathematical Modelling and Comparisons of Four Heuristic Optimization Algorithms for WCDMA Radio Network Planning.
33. A GaAs Device Isolation Technique by Liquid Phase Chemical-Enhanced Oxidation.
34. A systematic approach to robot inverse kinematics.
35. Advanced 0.25-0.18 /spl mu/m fully-planarized 6-level-interconnect CMOS technology for foundry manufacturing.
36. A fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturing.
37. Integrated NiSi defect reductions in 45nm node and beyond.
38. Evaluation of aluminum film properties and microstructure for replacement metal gate application at 28nm technology node.
39. Defect study of manufacturing feasible porous low k dielectrics direct polish for 45nm technology and beyond.
40. The investigation of galvanic corrosion in post-copper-CMP cleaning.
41. The investigation of electroplating deposited copper films for advanced VLSI interconnection.
42. Thermal Stability Improvement of Vertical Conducting Green Resonant-Cavity Light-Emitting Diodes on Copper Substrates.
43. Some policies for circuit allocation and their packet capacity in hybrid switching systems like FDDI-II
44. The investigation of galvanic corrosion in post-copper-CMP cleaning
45. Advanced 0.25-0.18 μm fully-planarized 6-level-interconnect CMOS technology for foundry manufacturing
46. A fully planarized 6-level-metal CMOS technology for 0.25-0.18 micron foundry manufacturing
47. A highly manufacturable 0.25 μm multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology
48. A systematic approach to robot inverse kinematics
49. A method to maintain phase-change memory pre-coding data retention after high temperature solder bonding process in embedded systems.
50. Flatband voltage tuning and EOT reduction for SiO2/HfO2/TiN gate stacks via lanthanum oxide capping layers using two different lanthanum precursors.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.