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The lattice misfit at the island-cap interface in two In0.15Ga0.85As p-i-n devices, with 5 layers of InAs quantum dots (QDs), was modified by depositing 2.1 and 3.2 ML of InAs while maintaining near identical capping layers. The device with 35 ± 3 nm island size distribution exhibited photoluminescence activity in the near infra-red range from 975 to 1150 nm while the device with 42 ± 12 nm size islands recorded lower PL intensity over a narrower range of 1000-1100 nm suggesting (a) increased island-cap interface misfit, (b) truncation of the islands, and (c) generation of structural defects.

A newly devised misfit management method was used to deftly balance the lattice strain in an InAs quantum dot (QD) based In 0.15 Ga 0.85 As p-i-n device. The photovoltaic behavior under AM0 conditions exhibited higher V oc and lower J sc in the QD-based device as compared to a control p-n device without quantum dots. To our knowledge, both of these observations are new and seemingly conflict with some of the current understanding of quantum-dot-based PV device physics. The PV behavior under infrared illumination confirms that the quantum-confined carriers of the InAs islands in the intrinsic region contribute to the photocurrent.

Graphene is a possible candidate for post CMOS applications and mobility is a material characteristic that has been utilized to gauge the quality of the material[1]. Mobility of exfoliated graphene transferred on SiO 2 has been reported to range from 2,000 to 25,000 cm2/V·s [1, 2]. The large variation is typically attributed to factors such as scattering by defects in the underlying substrate, residue from processing, charged impurity scattering and phonon scattering [3]. In most previous studies one of the primary assumptions made is that the mobility is independent of channel dimensions. In this study, we performed room temperature effective mobility measurements as a function of channel dimensions. The mobility exhibits clear channel length (L ch ) and width (W ch ) dependence and varies from less than 1,000 cm2/V·s to 7,000 cm2/V·s. Theoretical analysis of the conductivity (σ) in graphene devices as a function of W ch performed by Vasko et al [4]. is in agreement with our experimental results. Mobility values for back gated devices with well defined channel dimensions in literature [5] are seen to be consistent with the trend that we report here.

A stack of 10 InAs quantum dot layers has been incorporated into an In x Ga 1-x As(p doped)/InAs/In x Ga 1-x As(n doped) heterojunction semiconductor device using molecular beam epitaxy. Atomic force microscopy revealed quantum dots of sizes 20 to 50 nm and heights of 2 to 5 nm. The density was 2x1010 quantum dots per cm2 per layer. This device, when compared to In x Ga 1-x As (p doped)/In x Ga 1-x As(n doped) homojunction device with no InAs quantum dot layers, showed a 20 fold increase in the photocurrent density under 50 W lamp illumination however the open circuit voltage dropped. Exponential increase in the photocurrent might have been an effect of multiple exciton generation (carrier multiplication) due to discrete electronic wave functions in the nanometer sized InAs quantum dots.

The II–VI semiconductor cadmium selenide telluride CdSeTe was grown by MBE on silicon. The large lattice mismatch to the silicon was accommodated in smaller steps using a beryllium telluride - zinc telluride buffer layer. A CdTe film grown on this buffer had about three times narrower x-ray diffraction peak than a CdSe 0.40 Te 0.60 alloy. Photojunction devices were formed into mesa structures with n+Si / p+BeTe p-type bottom contacts and n-type CdSe top emitter layers, with thin (≪1 μm) CdSeTe base layers. The photocurrent of junctions with CdTe base layers was about an order of magnitude greater than those with the CdSe 0.40 Te 0.60 alloy, most likely due to short minority carrier lifetime in the ternary.

The Schottky barrier height at a metal/Si interface is ideally determined by the difference between metal work function and Si electron affinity for n-type Si. In reality, interface states between metal and Si pin the interface Fermi level, making the barrier height more or less independent of the ideal barrier height. We demonstrate that, by terminating dangling bonds on n-type Si(100) with a monolayer of Se, interface states are significantly reduced between metal and Si. As a result, low Schottky barriers are obtained for metals with low ideal barrier heights, such as Al and Cr. A negative Schottky barrier is demonstrated between Si and Ti, a metal commonly-used in the semiconductor industry. The negative Schottky barrier is thermally stable up to 400/spl deg/C. For metals with high ideal barrier heights, inconsistency is observed between ideal barrier height and measured barrier height even with Se passivation.