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Intracranial blood pressure can directly reflect the status of blood vessels in real time. However, it can only be estimated invasively using a microcatheter during craniotomy. Subharmonic-aided pressure estimation (SHAPE) is a promising technique for estimating cardiac pressures but mainly uses Sonazoid, whereas SHAPE using SonoVue is still in the early stages of development. The aim of this study was to optimize transcranial SHAPE using SonoVue by investigating the relationship between subharmonic signals and middle cerebral artery pressure (MCAP) (20–160 mmHg) in vitro. We examined the effect of acoustic output levels (peak negative pressures (PNPs) of 238, 346, and 454 kPa), time in suspension (time from reconstituting the suspension to extracting it: 0–30 min), and exposure to gas-equilibrated saline (3 min, 1 h, or original gas completely replaced by air) on the subharmonic-pressure relationship. A mean subharmonic amplitude over a 0.4 MHz bandwidth was extracted using a 5 MHz 12-cycle pulse. A PNP of 346 kPa elicited the best subharmonic sensitivity for assessing hydrostatic pressures up to 0.24 dB/mmHg, possibly because compression-only behavior no longer occurs at this pressure. Moreover, the expansion force is not large enough to offset the effects of hydrostatic pressure. A linear monotonic relationship between the subharmonic amplitude and hydrostatic pressure was only observed for just prepared SonoVue. Excessive exposure to gas-equilibrated saline also affected the subharmonic-pressure relationship. Therefore, just prepared SonoVue should be used, and the duration of the pressure estimation process should be strictly controlled. [ABSTRACT FROM AUTHOR]

With the popularity of social media (e.g., Facebook and Flicker), users can easily share their check-in records and photos during their trips. In view of the huge number of user historical mobility records in social media, we aim to discover travel experiences to facilitate trip planning. When planning a trip, users always have specific preferences regarding their trips. Instead of restricting users to limited query options such as locations, activities, or time periods, we consider arbitrary text descriptions as keywords about personalized requirements. Moreover, a diverse and representative set of recommended travel routes is needed. Prior works have elaborated on mining and ranking existing routes from check-in data. To meet the need for automatic trip organization, we claim that more features of Places of Interest (POIs) should be extracted. Therefore, in this paper, we propose an efficient Keyword-aware Representative Travel Route framework that uses knowledge extraction from users’ historical mobility records and social interactions. Explicitly, we have designed a keyword extraction module to classify the POI-related tags, for effective matching with query keywords. We have further designed a route reconstruction algorithm to construct route candidates that fulfill the requirements. To provide befitting query results, we explore Representative Skyline concepts, that is, the Skyline routes which best describe the trade-offs among different POI features. To evaluate the effectiveness and efficiency of the proposed algorithms, we have conducted extensive experiments on real location-based social network datasets, and the experiment results show that our methods do indeed demonstrate good performance compared to state-of-the-art works. [ABSTRACT FROM PUBLISHER]

In this paper, the thickness effect of an undoped Al0.23Ga0.77N inserted in the Mg-doped Al0.23Ga0.77N electron-blocking layer (EBL) on the characteristics of the ultraviolet light-emitting diodes (UV-LEDs) was analyzed. The results of secondary-ion-mass spectrometry clearly show that the concentration of Mg back-diffusion from the p-GaN and the Mg-doped EBL decreases with the thickness of an undoped EBL. The radiative recombination rate in the multiple quantum wells (MQWs) can be obviously enhanced after inserting an undoped EBL from the simulated results, and the sample with a 6-nm-thick undoped EBL has the highest radiative recombination rate. It is worth noticing that the hole carrier concentration in the MQWs increases with increasing the thickness of an undoped EBL. The UV-LED possesses 400% enhancement in the output power (at 20 mA) by inserting a 6-nm-thick undoped EBL. The significant enhancement is ascribed to the decrease of nonradiative recombination defects formed by Mg atoms and the increase of hole concentration in the MQWs. [ABSTRACT FROM AUTHOR]

A 400-nm near-ultraviolet InGaN/AlGaN light-emitting diode (LED) with a patterned distributed Bragg reflector (PDBR) mask is the subject of this paper. The design of the PDBR mask on the GaN/sapphire substrate attempts to reduce the threading dislocation density in the epitaxial template and enhance light extraction efficiency via the reflective behavior of the DBR. Under an injection current of 20 mA, the forward voltages of the PDBR and conventional LEDs were 3.51 and 3.52 V, respectively. This result indicates that the operating voltage of the PDBR LED does not arise by this PDBR mask design. In addition, the leakage current of the PDBR LED sample (1.36 nA at -5 V) is found to be lower than that of the conventional LED (11 nA). We also discovered that the light output power for the PDBR LED was approximately 39% higher (at 20 mA) than the conventional LED, and this significant improvement in performance is attributed not only to the GaN template crystalline quality reform but also due to the light extraction enhancement via the PDBR mask. [ABSTRACT FROM AUTHOR]

Bounding ellipsoid (BE) algorithms offer an attractive alternative to traditional training algorithms for neural networks, for example, backpropagation and least squares methods. The benefits include high computational efficiency and fast convergence speed. In this paper, we propose an ellipsoid propagation algorithm to train the weights of recurrent neural networks for nonlinear systems identification. Both hidden layers and output layers can be updated. The stability of the BE algorithm is proven. [ABSTRACT FROM AUTHOR]

An experimental methodology to find area-efficient compact layout rules to prevent latchup in bulk complimentary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new latchup prevention design by adding the additional internal double guard rings between input/output cells and internal circuits is first reported in the literature, and its effectiveness has been successfully proven in three different bulk CMOS processes. Through detailed experimental verification including temperature effect, the proposed methodology to extract compact layout rules has been established to save silicon area of CMOS ICs but still to have high enough latchup immunity. This proposed methodology has been successfully verified in a 0.5-µm nonsilicided, a 0.35-µm silicided, and a 0.25-µm silicided shallow-trench-isolation bulk CMOS processes. [ABSTRACT FROM AUTHOR]

Reports on the utilization of dynamic multilayer neural networks for nonlinear system online identification. Application of the passivity approach to access several stability properties of the neuro identifier; Establishment of the conditions for passivity, stability, asymptotic stability and input-to-state stability; Usability of the backpropagation algorithm with a modification term.

Presents information on a study which examined nonlinear system on-line identification via dynamic neural networks. Stability analysis for neural networks; Preliminaries; Neuro identification via passivity technique; Conclusion.

Focuses on a study in which the tuning algorithm for a class of dynamic neural networks has been derived. Stability properties of dynamic neural networks; Simulation of the dynamic neural network; Conclusion.

Proposes dynamic knowledge inference and learning under adaptive fuzzy Petri net (AFPN) framework. Formulation of adaptive fuzzy Petri net model; Development of back propagation algorithm for knowledge learning under generalized condition; Account on weighted fuzzy production rule; Applicability of AFPN to knowledge representation and reasoning.

Focuses on the characterization of grain boundaries in yttrium barium copper oxide bicrystal junctions. Thin film preparation and devices fabrication; Current-voltage characteristics; Sequential destructive deterioration of the bicrystal junction.

Conventional interleaved half-bridge flyback converters can recycle the leakage energy stored in leakage inductance to clamp the voltage across the main power switches at a dc input voltage. However, such converters still suffer from high switching losses, especially turn-off losses. In this paper, a novel turn-off zero-current-transition (ZCT) circuit is proposed for reducing the turn-off switching losses. The proposed ZCT interleaved half-bridge flyback converter operates at a fixed frequency without increasing the voltage stresses of the main switches. To verify the design, a laboratory prototype is implemented with 100 kHz, an input voltage of 400 V, and an output voltage of 24 V/480 W. The experimental results reveal that the proposed converter at full load and 20% load has efficiencies of 93.05% and 89.06%, yielding efficiency improvements of 1.17% and 4.12%, respectively, compared with the conventional interleaved half-bridge flyback converter. [ABSTRACT FROM AUTHOR]

A time-to-digital converter (TDC) plays an important role in time interval measurement. Among various TDC structures, the Vernier-based TDC (VTDC) is promising because the time resolution of it depends on the frequency difference between the oscillators, not on the absolute oscillating frequency values. However, the oscillators used in the conventional VTDC require complicated calibration procedures. This makes the TDC system complex. This paper employs a new soft-injection-locked ring oscillator as the clock source for the VTDC. The proposed oscillator can oscillate immediately and accurately right after the triggering signal arrives. The TDC structure employing the purposed oscillators is verified by the TSMC 0.18- \mum CMOS process. The measured differential nonlinearity is within \pm0.4~LSB and the measured integral nonlinearity is within \pm0.8~LSB . The power consumption is 27.8 mW. The chip's core area is around 0.095 mm^2 . When the supply voltage varies from 1.75 to 1.85 V, the resolution deviation is less than \pm0.18~LSB . [ABSTRACT FROM PUBLISHER]

The oxidation rate of SiC can be greatly enhanced by pre-amorphization ion-implantation (PAI), and the PAI process has been employed to form the LOCal Oxidation of SiC (LOCOSiC) structure for device isolation in SiC integrated circuits (ICs). This work presents the study on the defect layer below the thermally grown SiO2 and the impact of the defect layer on devices. The deep-level transient spectroscopy (DLTS) analysis reveals that the defect layer consists lots of C vacancies and Si vacancies. The leakage current of the edge-intensive N+/P-junction exhibits stronger temperature dependence than that of the P+/N-junction. This result confirms that C vacancy is an effective lifetime killer in n-type SiC, but not in p-type SiC. Although these defects increase the leakage current of the edge-intensive SiC N+/P-junction by 42 times at 150 °C compared with the junction with conventional chemical vapor deposited (CVD) field oxide (FOX), the leakage current is still much lower than the required OFF-state current of ICs. The defect layer has high resistance, and it is hard to let the SiC surface into inversion state so that the threshold voltage of the field MOSFET is higher than ±24 V. [ABSTRACT FROM AUTHOR]

This brief is concerned with the global robust exponential stability of a class of interval Cohen-Grossberg neural networks with both multiple time-varying delays and continuously distributed delays. Some new sufficient robust stability conditions are established in the form of state transmission matrix, which are different from the existing ones. Furthermore, a sufficient condition is also established to guarantee the global stability for this class of Cohen-Grossberg neural networks without uncertainties. Three examples are used to show the effectiveness of the obtained results. [ABSTRACT FROM AUTHOR]

In this paper, we introduce a new skeleton pruning method based on contour partitioning. Any contour partition can be used, but the partitions obtained by Discrete Curve Evolution (DCE) yield excellent results. The theoretical properties and the experiments presented demonstrate that obtained skeletons are in accord with human visual perception and stable, even in the presence of significant noise and shape variations, and have the same topology as the original skeletons. In particular, we have proven that the proposed approach never produces spurious branches, which are common when using the known skeleton pruning methods. Moreover, the proposed pruning method does not displace the skeleton points. Consequently, all skeleton points are centers of maximal disks. Again, many existing methods displace skeleton points in order to produces pruned skeletons. [ABSTRACT FROM AUTHOR]

One method to enhance electrostatic discharge (ESO) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18-μm salicided CMOS process' is investigated by experimental testchips. The second breakdown current (It2) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated. [ABSTRACT FROM AUTHOR]

Studies the effects of modulation schemes on the performance of directly coupled high temperature superconducting quantum interference device (SQUID) magnetometers. Design and fabrication of the SQUID devices; Modulation efficiency; Coupling of modulation fluxes.

Continually disclosed vulnerabilities reveal that traditional computer architecture lacks the consideration of security. This article proposes a security-first architecture, with an Active Security Processor (ASP) integrated to conventional computer architectures. To reduce the attack surface of ASP and improve the security of the whole system, the ASP is physically isolated from Computation Processor Units (CPU) with an asymmetric address space, which enables both ASP and CPU to run their operating system and applications independently in their own memory space. Furthermore, the ASP, which has the highest privilege (Super Root) of the whole system, possesses two advantageous features. First, the ASP can efficiently access all CPU resources and collect multi-dimensional information to monitor malicious behaviors, meanwhile, the CPU cannot access the ASP's private resources in any way. Second, instead of being scheduled by CPUs, the ASP can actively manage the security mechanisms employed in either CPUs or the ASP. Based on the security-first architecture, we introduce several typical security tasks running on ASP. With different considerations in terms of system overhead, complexity and performance, we also explore four typical system-level implementations for integrating the ASP to the security-first architecture. The first-generation ASP was designed and implemented based on the 40nm technology, and a security computer system was implemented based on it. Evaluations on this real hardware platform demonstrate that the security-first architecture can protect the system effectively with minor performance impacts on computing workloads. [ABSTRACT FROM AUTHOR]

The progress of light-emitting-diode (LED) development based on nitride nanocolumn (NC) growth, including InGaN/GaN quantum-well (QW) growth on NCs and regularly arranged GaN NC growth, is first reviewed. Then, the coalescence-overgrowth results based on patterned GaN NC growth are introduced. The overgrowth quality dependence on NC cross-sectional size and NC spacing size is discussed. Generally, a smaller NC dimension and spacing size lead to higher overgrowth quality, including lower threading dislocation (TD) density and larger lateral domain size. Next, the emission enhancement results blue- and green-emitting InGaN/GaN QW and LED structures based on NC growth and coalescence overgrowth are presented. Significant enhancements (up to ∼100% output intensity increase in a blue LED) are demonstrated. For LED applications, the TD density reduction in an overgrown GaN template can more effectively enhance the emission efficiency of a blue LED, when compared with a green LED. [ABSTRACT FROM AUTHOR]

A 2.4/5.7-GHz dual-band Weaver-Hartley architecture, using 0.18-μm CMOS technology, is demonstrated in this paper. The 2.4-GHz signal is set to be the image signal when the desired signal is at 5.7 GHz, and vice versa. Since the Weaver and Hartley systems are combined into this architecture, the demonstrated architecture rejects not only the first image signal, but also the secondary image signal. The image-rejection ratios of the first image signal and the secondary image signal are better than 40 and 46 dB, respectively. In this paper, a diagrammatic explanation is employed to obtain the image-rejection mechanisms of the Weaver-Hartley architecture. [ABSTRACT FROM AUTHOR]

A new adjustable insulated gate bipolar transistor (IGBT) with Si/SiGe heterojunction collector structures is proposed to improve the operation speed and decrease the turnoff power loss by suppressing the tail-current. SiGe collector provides low contact resistance without consequently sacrificing turnoff losses, and also acts to suppress hole-injection into drift region during on-state and accelerate the clear sweep of the holes when the device is cutoff. On the other hand, turn-on voltage loss is increased due to the use of SiGe collector. This drawback can be minimized by using lower percentages of Ge in SiGe, since the potential barrier height at the Si/SiGe junction is controlled by the percentage of Ge in SiGe, which means the proposed [GBT can be tuned freely to meet different needs by means of changing the percentage of Ge region in the SiGe. Further, the proposed IGBT exhibits a more superior on-state/switching tradeoff relation when compared to the conventional IGBT. Two-dimensional device and circuit mixed-mode simulations are also performed to offer valuable information about the internal dynamical mechanisms of these devices, thus improving the understanding of device performance in SiGe collector applications. [ABSTRACT FROM AUTHOR]

For the first time, a novel plugged p+ collector is proposed for the insulated gate bipolar transistor (IGBT) and evaluated in detail by using two-dimensional numerical simulations as an effective method to control the collector injection efficiency and enhance the turn-off performance. Extensive simulations indicate the turn-off time of this device is reduced and the forward blocking capability is improved significantly compared to the conventional IGBT. Most importantly, the proposed IGBT breaks the deadlock between the low on-state energy loss and fast speed by engineering the whole heavy-doped p+ collector into a high-injection-efficiency heavy-doped p+ region and a low-injection-efficiency lightly doped p- region to offer a more superior on-state/switching tradeoff. The heavily doped p+ region assures an optimum level of conductivity modulation required for a reasonable on-state voltage drop in the n- drift region, while the lightly doped p- region accelerates the device's turn-off. These advantages make this device an attractive candidate for high-frequency high-power applications. [ABSTRACT FROM AUTHOR]