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In this paper, the peak-to-peak filtering problem is studied for a class of networked nonlinear systems. The nonlinear physical plant is represented by the Takagi–Sugeno fuzzy system. Assume that the data packet dropout phenomenon occurs when the measurement output signal and the performance output signal of the nonlinear systems are transmitted by the digital communication channel. Two stochastic variables satisfying the Bernoulli random binary distribution are used to model this phenomenon. The motive of this paper is to design a peak-to-peak filter such that the filtering error system is stochastically stable and the prescribed peak-to-peak performance index is guaranteed. The developed theoretical results for designing a peak-to-peak filter are expressed in the form of linear matrix inequalities. Finally, a simulation example is presented to illustrate the validity of theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper investigates the peak-to-peak filtering problem for a class of networked nonlinear dc motor systems with quantization. The nonlinear dc motor system is modeled by a Takagi–Sugeno (T–S) fuzzy model. Consider that the measurement output signal and the performance output signal of the system are quantized by two static quantizers before being transmitted by the digital communication channel, respectively. Attention is focused on the design of a peak-to-peak filter such that the filtering error system is asymptotically stable and satisfies the prescribed peak-to-peak filtering performance index. Sufficient conditions for such a peak-to-peak filter are expressed in the form of linear matrix inequalities. Finally, an illustrative simulation is given to show the effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chip’s maximum operating speed. This learned model can be included in an auto test equipment (ATE) software to predict the chip speed for speed binning. Such a speed-binning method can avoid the use of applying any functional test and, hence, result in a third-order test time reduction with a limited portion of chips placed into a slower bin compared with the conventional functional-test binning. This paper further presents a novel built-in self-speed-binning system, which embeds the learned chip-speed model with a built-in circuit such that the chip speed can be directly calculated on-chip without going through any offline ATE software, achieving a fourth-order test-time reduction compared with the conventional speed binning. The experiments were conducted based on 360 test chips of a 28-nm, 0.9 V, 1.6-GHz mobile-application system-on-chip. [ABSTRACT FROM PUBLISHER]

A clock skew-compensation and duty-cycle correction circuit (CSADC) is used as the second-level clock distributing circuit to align a system global clock while maintaining a 50% duty cycle. A power-efficient, range-unlimited, and accuracy-enhanced CSADC, designed mainly with a new delay-interleaving and -recycling technique that mitigates operating frequency limitations while keeping overhead costs low, is proposed in this paper. Our preliminary research results prove the feasibility of the proposed technique and show that the operating frequency ranges from 110 MHz to 1.75 GHz, with the corrected duty cycle varying from 51.2% to 48.9% based on 0.18- $\mu $ m CMOS technology. Meanwhile, the lock-in time, static phase error, and power consumption are, respectively, 26 clock cycles, 4.2 ps, and 5.58 mW at 1.75 GHz. [ABSTRACT FROM AUTHOR]

This brief presents a novel keeper technique for high-performance and high-noise-immunity wide fan-in dynamic circuits. Two major innovations are proposed, i.e., the adaptive pseudo dual keeper technique, which can either significantly reduce evaluation contention or maximize immediate noise immunity through a simple single keeper structure, and the diode-connected self-biasing circuit to minimize the static current of the adaptive pseudo dual keeper. Both these original design concepts help to achieve higher performance and lower power consumption while maintaining the high noise immunity. Several wide fan-in dynamic gates were designed using UMC 90-nm 1-V technology. Our simulation results demonstrate that using the proposed keeper technique, the 32-bit or gate and multiplexer can achieve delay reductions of at least 22% and 17.7%, respectively, for the same unity-gain direct-current noise (UGDN)-immunity requirement, as compared with conventional keeper techniques. Meanwhile, power dissipation is reduced by up to 55.3% due to the simple keeper structure and contention reduction. The simulations also show that circuits with the proposed keeper show small variations in delay and power consumption over a wide range of noise-immunity requirements, e.g., they vary by only 2.1% and 3.2% for a 32-bit multiplexer with 0.24- to 0.32-V UGDN levels. [ABSTRACT FROM PUBLISHER]